A New Investigation of Data Retention Time in Truly Nanoscaled DRAMs

Kim, Kinam; Lee, Jooyoung

doi:10.1109/led.2009.2023248

Cited by 111 publications

(7 citation statements)

References 7 publications

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“…Furthermore, it has been projected that as a DRAM technology shrinks down to a nanoscale, the tail distribution of the data retention time will be separated with main one. 8) It seems that the phenomenon begins to be appeared slightly as shown in Fig. 11.…”

Section: Data Retention Characteristicsmentioning

confidence: 87%

“…The correlations contain the contradiction with the normal prediction which the junction LKG is main mechanism for the normal healthy cells and the GIDL current is for the leaky cells to determine the data retention time in 3D recess channel structure such as the S-Fin transistor especially adopting NWL scheme. 4,8) For the further analysis of the retention behavior, the charge pumping test was approached to estimate an energy distribution of interface-state-density by applying trapezoidal pulse train in a gate terminal of a 4 Â 10 4 cell array pattern (Fig. 9).…”

Section: Data Retention Characteristicsmentioning

confidence: 99%

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Data Retention Characteristics for Gate Oxide Schemes in Sub-50 nm Saddle-Fin Transistor Dynamic-Random-Access-Memory Technology

Ryu¹,

Yoo²,

Choi

et al. 2011

Jpn. J. Appl. Phys.

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A data retention time has been investigated for various gate oxide schemes of saddle-fin (S-Fin) transistor dynamic random access memory (DRAM). The interface traps strongly affected the data retention time which was not clearly explained with a gate-induced-drain-leakage (GIDL) current as well as a junction leakage current. Despite the lower GIDL current by the thicker side-wall oxide of a dry oxidation scheme than a radical scheme, the degradation of the retention time was originated from the high interface-trap density (D it ). It is worthwhile to note that the D it as well as the GIDL current is a still meaning parameter to analyze the data retention time. #

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Section: Data Retention Characteristicsmentioning

confidence: 87%

Section: Data Retention Characteristicsmentioning

confidence: 99%

Data Retention Characteristics for Gate Oxide Schemes in Sub-50 nm Saddle-Fin Transistor Dynamic-Random-Access-Memory Technology

Ryu¹,

Yoo²,

Choi

et al. 2011

Jpn. J. Appl. Phys.

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show abstract

“…Therefore, when a designer prefers lower refresh rates, a φ s that would make the read-mechanism BTBT would be desirable. A longer RT can improve the efficiency of the system by reducing the overhead of the refresh cycle [35]. However, if a higher read-current and SM is required then a φ s that would make the read-mechanism drift-diffusion would be desirable.…”

Section: B Impact Of Source Workfunction φ Smentioning

confidence: 99%

Dopingless 1T DRAM: Proposal, Design, and Analysis

James

Saurabh

2019

IEEE Access

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In this paper, we have proposed a dopingless 1T DRAM (DL-DRAM) that utilizes the charge plasma concept. The proposed device employs a misaligned double-gate architecture to store holes and differentiates between the two logic states. The source, drain, backgate, and frontgate workfunctions are optimized to achieve the required concentration profiles in an intrinsic silicon body. Using TCAD simulations, we have analyzed the read/write mechanism in the device. Our study shows that the mechanism of current transport during reading operation depends strongly on the source workfunction. When the source workfunction is less than 4.5 eV the transport mechanism during reading is dominated by driftdiffusion. However, when the source workfunction is greater than 4.5 eV , the transport mechanism during read is dominated by band-to-band tunneling (BTBT). In general, when the dominant mechanism of current transport is BTBT, the retention time and the read-1/0 current ratio is higher, and the sense margin is lower in the case in which the dominant mechanism of current transport is drift-diffusion. Due to the avoidance of doping, the proposed DL-DRAM is expected to be free from random dopant fluctuation. Moreover, high temperature annealing processes required after ion implantation can be avoided. The lower thermal requirements of a DL-DRAM opens the possibility of fabricating DRAMs using processes which are compatible with bio-materials and opto-electronics and in ensuring bottom MOSFET and interconnects preservation in 3D VLSI integration. INDEX TERMS DRAM, dopingless, sense margin, retention time, charge plasma.

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“…Recent studies on custom FPGA boards have shown that the retention time of cells varies considerably across and within a DRAM chip. Typically, only a very small number of cells need to be refreshed once every T R E F W = 64 m s (Bhati et al, 2016; Jung et al, 2016b; Kinam Kim and Jooyoung Lee, 2009; Liu et al, 2013). To verify this observation on typical server environments, we have performed experiments on various 8 GB DDR3 DIMMs of a premium vendor, using our experimental prototype and a memory tester with random and uniformly distributed data patterns designed to detect the retention time of DRAM bit cells.…”

Section: Background and Motivationmentioning

confidence: 99%

Dare

Chalios

Georgakoudis

Tovletoglou

et al. 2017

The International Journal of High Performance Computing Applica

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Power consumption and reliability of memory components are two of the most important hurdles in realizing exascale systems. Dynamic random access memory (DRAM) scaling projections predict significant performance and power penalty due to the conventional use of pessimistic refresh periods catering for worst-case cell retention times. Recent approaches relax those pessimistic refresh rates only on ''strong'' cells, or build on application-specific error resilience for data placement. However, these approaches cannot reveal the full potential of a relaxed refresh paradigm shift, since they neglect additional application resilience properties related to the inherent functioning of DRAM. In this article, we elevate Refresh-by-Access as a first-class property of application resilience. We develop a complete, non-intrusive system stack, armed with low-cost Data-Access Aware Refresh (DARE) methods, to facilitate aggressive refresh relaxation and ensure non-disruptive operation on commodity servers. Essentially, our proposed access-aware scheduling of application tasks intelligently amplifies the impact of the implicit refresh of memory accesses, extending the period during which hardware refresh remains disabled, while limiting the number of potential errors, hence their impact on an application's output quality. The stack, implemented on an off-the-shelf server and running a full-fledged Linux OS, captures for the first time the intricate time-dependent system and data interactions in the presence of hardware errors, in contrast to previous architectural simulations approaches of limited detail. Results demonstrate that by applying DARE, it is possible to completely disable hardware refresh, with minor quality loss that ranges from 2% to 18%.

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A New Investigation of Data Retention Time in Truly Nanoscaled DRAMs

Cited by 111 publications

References 7 publications

Data Retention Characteristics for Gate Oxide Schemes in Sub-50 nm Saddle-Fin Transistor Dynamic-Random-Access-Memory Technology

Data Retention Characteristics for Gate Oxide Schemes in Sub-50 nm Saddle-Fin Transistor Dynamic-Random-Access-Memory Technology

Dopingless 1T DRAM: Proposal, Design, and Analysis

Dare

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