Data Retention Characteristics for Gate Oxide Schemes in Sub-50 nm Saddle-Fin Transistor Dynamic-Random-Access-Memory Technology

Abstract

A data retention time has been investigated for various gate oxide schemes of saddle-fin (S-Fin) transistor dynamic random access memory (DRAM). The interface traps strongly affected the data retention time which was not clearly explained with a gate-induced-drain-leakage (GIDL) current as well as a junction leakage current. Despite the lower GIDL current by the thicker side-wall oxide of a dry oxidation scheme than a radical scheme, the degradation of the retention time was originated from the high interface-trap density (D it ). It is worthwhile to note that the D it as well as the GIDL current is a still meaning parameter to analyze the data retention time. #

Exploring the magnetic, electric and magnetodielectric properties of (1 − x)Ba0.9Ni0.1Ti0.9Mn0.1O3–xCo0.9Mn0.1Fe1.9V0.1O4 multiferroic composites

“…This effect increases the interface area between ferroic phases and decreases porosity. 36 This structural change of the material may optimise strain transfer from the magnetic CF phase to the ferroelectric BT phase.…”