A New Method for Revealing Striations in High-Resistive Floating-Zone Silicon Crystals

Köck, Anton; Boonen, P.G.T.

doi:10.1149/1.2404450

Cited by 9 publications

(3 citation statements)

References 10 publications

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“…We have, however, schematically outlined the problem as shown in Fig. 5, which is based, in part, on recent work of Pomerantz (17) and de Kock (8,18,19).…”

Section: Discussionmentioning

confidence: 99%

Elimination of Oxidation‐Induced Stacking Faults by Preoxidation Gettering of Silicon Wafers: I . Phosphorus Diffusion‐Induced Misfit Dislocations

Rozgonyi¹,

Petroff²,

Read³

1975

J. Electrochem. Soc.

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In the present paper a preoxidation gettering procedure (called POGO) is described which prevents the formation and/or activation of stacking fault nucleation sites during oxidation. In this way the stacking faults and their possible device degrading influences are eliminated at the start of a processing schedule. In addition, the gettering medium is retained through all subsequent high temperature processing, thereby continuing to suppress the formation of stacking faults. The gettering of the nucleation sites, whether they be process induced, such as impurity precipitation, or native to the original crystal growth, such as vacancies or impurities, is achieved by the controlled introduction of interfacial misfit dislocations on the back side of the wafer. The dislocations interact with the stacking fault nucleation sites such that the nuclei diffuse from the active device side of the wafer to the line defects which are confined to within a few microns of the back surface.

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“…We have, however, schematically outlined the problem as shown in Fig. 5, which is based, in part, on recent work of Pomerantz (17) and de Kock (8,18,19).…”

Section: Discussionmentioning

confidence: 99%

Elimination of Oxidation‐Induced Stacking Faults by Preoxidation Gettering of Silicon Wafers: I . Phosphorus Diffusion‐Induced Misfit Dislocations

Rozgonyi¹,

Petroff²,

Read³

1975

J. Electrochem. Soc.

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“…These swirls defects are undesirable in the IC fabrication process (Garavaglia and Guthche 1972), and cause variations in the minority carrier lifetime. The mechanisms of the formation and elimination swirls have been reported by de Kock and co-workers (de Kock 1970, 1971, de Kock and Boonen 1972, de Kock et a1 1974. There are two kinds of vacancy cluster in swirl defects: A and B, and the B type has a smaller volume than the A type.…”

Section: A Usami Y Fujii and K Moriokamentioning

confidence: 61%

The effect of swirl defects on the minority carrier lifetime in heat-treated silicon crystals

Usami¹,

Fujii²,

Monoka³

1977

J. Phys. D: Appl. Phys.

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The changes in the minority carrier lifetime for heat-treated silicon crystals at relatively low temperatures (200-600 degrees C) were observed. The minority carrier life-time of n-type floating-zoned swirl-free and swirl-containing, n-type Czochralski-grown swirl-containing and p-type floating-zoned swirl-containing, silicon crystals abruptly decreased between 400 and 500 degrees C, and the activation energy for defect formation in this temperature range was about 1.3 eV in these crystals. However, in p-type floating-zoned swirl-free silicon crystals, the behaviour of the minority carrier lifetime was different; there was an increase in the lifetime centred around 350 degrees C and an abrupt decrease above 600 degrees C. The defect formation energies were 1.39 eV between 300 and 350 degrees C, 3.30 eV between 350 and 400 degrees C, and 3.25 eV between 580 and 620 degrees C. The influences of swirl defects on the changes in the minority carrier lifetime during the heat treatments are also described.

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“…Thus, in general, less perfect regions etch more rapidly than high quality crystalline regions. Etchants are also used to reveal resistivity striations (38,(140)(141)(142) and swirls in silicon and in other semiconductor materials. Copper displacement plating has been used to delineate imperfections in polished silicon substrates (143).…”

Section: Electrochemical Techniques For Control Of Semiconductor Devi...mentioning

confidence: 99%

Applications of Electrochemistry to Fabrication of Semiconductor Devices

Schnable

Schmidt

1976

J. Electrochem. Soc.

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This paper reviews some of the principal applications of electrochemistry to fabrication of semiconductor devices. Some of the electrochemical techniques used in fabrication of early semiconductor devices, such as chemical polishing, plating of contacts, dislocation etches, and junction delineation techniques continue to be used in manufacturing of present‐day devices. Principal newer uses of electrochemistry are in anisotropic etching of patterns in single crystal Si, in preferential etching of layers of a certain conductivity type or doping level without dissolution of an underlying (or adjacent) layer of Si of different type or doping level, in anodization of aluminum metallization on Si devices, and in Au plating for conductive layers in several types of silicon devices. A wide variety of other electrochemical techniques are being used in material and device characterization, and in fabrication of developmental‐type devices.

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A New Method for Revealing Striations in High-Resistive Floating-Zone Silicon Crystals

Cited by 9 publications

References 10 publications

Elimination of Oxidation‐Induced Stacking Faults by Preoxidation Gettering of Silicon Wafers: I . Phosphorus Diffusion‐Induced Misfit Dislocations

Elimination of Oxidation‐Induced Stacking Faults by Preoxidation Gettering of Silicon Wafers: I . Phosphorus Diffusion‐Induced Misfit Dislocations

The effect of swirl defects on the minority carrier lifetime in heat-treated silicon crystals

Applications of Electrochemistry to Fabrication of Semiconductor Devices

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