A new perspective on processing-in-memory architecture design

Zhang, Dong Ping; Jayasena, Nuwan; Lyashevsky, Alexander; Greathouse, Joseph L.; Meswani, Mitesh R.; Nutter, Mark; Ignatowski, Mike

doi:10.1145/2492408.2492418

Cited by 36 publications

(35 citation statements)

References 8 publications

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“…Similarly, many configurations of PIM (processing-in-memory) architectures have been envisioned in [17,16]. Projections showed promising results to address data movement bottlenecks and overheads, however the paper states that PIM can only be adopted with appropriate programming models and strong support from the compiler, runtime and operating system.…”

Section: Related Workmentioning

confidence: 99%

Data access optimization in a processing-in-memory system

Sura

Jacob

Chen

et al. 2015

Proceedings of the 12th ACM International Conference on Computing Frontiers

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The Active Memory Cube (AMC) system is a novel heterogeneous computing system concept designed to provide high performance and power-efficiency across a range of applications. The AMC architecture includes general-purpose host processors and specially designed in-memory processors (processing lanes) that would be integrated in a logic layer within 3D DRAM memory. The processing lanes have large vector register files but no power-hungry caches or local memory buffers. Performance depends on how well the resulting higher effective memory latency within the AMC can be managed. In this paper, we describe a combination of programming language features, compiler techniques, operating system interfaces, and hardware design that can effectively hide memory latency for the processing lanes in an AMC system. We present experimental data to show how this approach improves the performance of a set of representative benchmarks important in high performance computing applications. As a result, we are able to achieve high performance together with power efficiency using the AMC architecture.

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Section: Related Workmentioning

confidence: 99%

Data access optimization in a processing-in-memory system

Sura

Jacob

Chen

et al. 2015

Proceedings of the 12th ACM International Conference on Computing Frontiers

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“…Since off-chip data movement is a major bottleneck for computer systems [15], the main goals are usually increasing performance and reducing energy consumption. Table 2 presents an overview of the characteristics of the related work presented in this section and our proposal (MVX).…”

Section: Related Workmentioning

confidence: 99%

Opportunities and Challenges of Performing Vector Operations inside the DRAM

Alves

Santos

Diener

et al. 2015

Proceedings of the 2015 International Symposium on Memory Systems

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In order to overcome the low memory bandwidth and the high energy costs associated with the data transfer between the processor and the main memory, proposals on near-data computing started to gain acceptance in systems ranging from embedded architectures to high performance computing. The main previous approaches propose application specific hardware or require a large amount of logic. Moreover, most proposals require algorithm changes and do not make use of the full parallelism available on the DRAM devices. These issues limits the adoption and the performance of near-data computing. In this paper, we propose to implement vector instructions directly inside the DRAM devices, which we call the Memory Vector Extensions (MVX). This balanced approach reduces data movement between the DRAM to the processor while requiring a low amount of hardware to achieve good performance. Comparing to current vector operations present on processors, our proposal enable performance gains of up to 97× and reduces the energy consumption by up to 70× of the full system.

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“…It is worth noting that previous research focused on PNM designs which did not feature a cache hierarchy [6,9]. However, recent studies include at least one level of cache hierarchy, as the idea that PNM would be expected to handle general purpose applications is gaining support [13,22,23].…”

Section: Pnm Executionmentioning

confidence: 99%

Understanding Energy Aspects of Processing-near-Memory for HPC Workloads

Kim

Yalamanchili

Rodrigues

2015

Proceedings of the 2015 International Symposium on Memory Systems

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Interests in the concept of processing-near-memory (PNM) have been reignited with recent improvements of the 3D integration technology. In this work, we analyze the energy consumption characteristics of a system which comprises a conventional processor and a 3D memory stack with fully-programmable cores. We construct a high-level analytical energy model based on the underlying architecture and the technology with which each component is built. From the preliminary experiments with 11 HPC benchmarks from Mantevo benchmark suite, we observed that misses per kilo instructions (MPKI) of last-level cache (LLC) is one of the most important characteristics in determining the friendliness of the application to the PNM execution.

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A new perspective on processing-in-memory architecture design

Cited by 36 publications

References 8 publications

Data access optimization in a processing-in-memory system

Data access optimization in a processing-in-memory system

Opportunities and Challenges of Performing Vector Operations inside the DRAM

Understanding Energy Aspects of Processing-near-Memory for HPC Workloads

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