A new statistical approach for fault-tolerant VLSI systems

Stapper, C.H.

doi:10.1109/ftcs.1992.243565

Cited by 15 publications

(12 citation statements)

References 20 publications

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“…A 10% initial yield is assumed for designs without redundant HBISR circuitry. This or similar values were also assumed in [17], [26], and [27]. The relative productivity is the relative yield increase divided by the relative area increase.…”

Section: Resultsmentioning

confidence: 71%

“…For these calculations, we used Stapper's yield formula [26], which calculates the probability that exactly out of modules operate correctly for a given value of the variability parameter and single module yield A slight modification is made to the formula to take into account units of largely different areas.…”

Section: Resultsmentioning

confidence: 99%

“…In general as is increased, the improvement in the productivity can give diminishing returns, and can even produce lower productivity [26]. An interesting issue for HBISR design is the actual selection of the value of which gives the optimal effective yield, as a tradeoff between resilience to failure and hardware overhead.…”

Section: B Varying Levels Of Fault Tolerancementioning

confidence: 99%

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Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's

Guerra

Potkonjak

Rabaey

1998

IEEE Trans. VLSI Syst.

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Abstract-In this paper, behavioral-level synthesis techniques are presented for the design of reconfigurable hardware. The techniques are applicable for synthesis of several classes of designs, including 1) design for fault tolerance against permanent faults, 2) design for improved manufacturability, and 3) design of application specific programmable processors (ASPP's)-processors designed to perform any computation from a specified set on a single implementation platform. This paper focuses on design techniques for efficient built-in self-repair (BISR), and thus directly addresses the former two applications. Previous BISR techniques have been based on replacing a failed module with a backup of the same type. We present new heterogeneous BISR methodologies which remove this constraint and enable replacement of a module with a spare of a different type. The approach is based on the flexibility of behavioral-level synthesis to explore the design space. Two behavioral synthesis techniques are developed; the first method is through assignment and scheduling, and the second utilizes transformations. Experimental results verify the effectiveness of the approaches.

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Section: Resultsmentioning

confidence: 71%

Section: Resultsmentioning

confidence: 99%

Section: B Varying Levels Of Fault Tolerancementioning

confidence: 99%

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Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's

Guerra

Potkonjak

Rabaey

1998

IEEE Trans. VLSI Syst.

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“…Design errors can also cause a device to stop functioning in response to rate sequences of inputs (e.g., due to a power density surge in a small part of design). For this type of model, we follow the gamma-distribution Stapper fault model [25]. The model is applicable on any integrated In the remainder of this section, we elaborate on technical details related to the two fault models' reliability calculations.…”

Section: B Synthesis Methodsmentioning

confidence: 99%

“…To calculate reliability for correlated faults, we started from the following formula [25]: The formula calculates the probability that exactly out of identical modules operate correctly for a given value of the variability parameter and single CLB reliability The parameter indicates the assumed or the measured probability of clustered faults. Small values of imply high levels of clustering.…”

Section: B Stapper's Fault Modelmentioning

confidence: 99%

Low overhead fault-tolerant FPGA systems

Lach

Mangione-Smith

Potkonjak

1998

IEEE Trans. VLSI Syst.

124

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Fault-tolerance is an important system metric for many operating environments, from automotive to space exploration. The conventional technique for improving system reliability is through component replication, which usually comes at significant cost: increased design time, testing, power consumption, volume, and weight. We have developed a new faulttolerance approach that capitalizes on the unique reconfiguration capabilities of field programmable gate arrays (FPGA's). The physical design is partitioned into a set of tiles. In response to a component failure, a functionally equivalent tile that does not rely on the faulty component replaces the affected tile. Unlike application specific integrated circuit (ASIC) and microprocessor design methods, which result in fixed structures, this technique allows a single physical component to provide redundant backup for several types of components. Experimental results conducted on a subset of the MCNC benchmarks demonstrate a high level of reliability with low timing and hardware overhead.Index Terms-Field programmable gate array (FPGA), faulttolerance.

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A defect- and fault-tolerant architecture for nanocomputers

Han

Jonker

2003

Nanotechnology

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Both von Neumann’s NAND multiplexing, based on a massive duplication of imperfect devices and randomized imperfect interconnects, and reconfigurable architectures have been investigated to come up with solutions for integrations of highly unreliable nanometre-scale devices. In this paper, we review these two techniques, and present a defect- and fault-tolerant architecture in which von Neumann’s NAND multiplexing is combined with a massively reconfigurable architecture. The system performance of this architecture is evaluated by studying its reliability, i.e. the probability of system survival. Our evaluation shows that the suggested architecture can tolerate a device error rate of up to 10−2, with multiple redundant components; the structure is efficiently robust against both permanent and transient faults for an ultra-large integration of highly unreliable nanometre-scale devices.

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A new statistical approach for fault-tolerant VLSI systems

Cited by 15 publications

References 20 publications

Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's

Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's

Low overhead fault-tolerant FPGA systems

A defect- and fault-tolerant architecture for nanocomputers

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