2022
DOI: 10.1049/cds2.12127
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A novel buffering fault‐tolerance approach for network on chip (NoC)

Abstract: Network-on-Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication between many cores. NoC is a network-based communication subsystem on an integrated circuit, most typically between modules in a system on a chip (SoC). Designing a reliable NoC against failures that can prevent failure using some measures or preventing error or system failure while failure happens and proper performance became a significant concern. For a reliable design against failures, first, the system sh… Show more

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Cited by 9 publications
(3 citation statements)
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“…There are various levels and protocols of system interaction: from the hardware implementation level technologies to program levels of the description of protocols and data structures. As NoC is conceptually a data network implemented inside the chip to organize data transfer between IP blocks and other NoC components, it is possible to compare the NoC structure and the tasks solved by its components with the OSI network model (Figure 4) [12], [13].…”
Section: B Noc Model and Stages Of Its Developmentmentioning
confidence: 99%
“…There are various levels and protocols of system interaction: from the hardware implementation level technologies to program levels of the description of protocols and data structures. As NoC is conceptually a data network implemented inside the chip to organize data transfer between IP blocks and other NoC components, it is possible to compare the NoC structure and the tasks solved by its components with the OSI network model (Figure 4) [12], [13].…”
Section: B Noc Model and Stages Of Its Developmentmentioning
confidence: 99%
“…Experimental results show that this method not only restrains multi-scale noise but also increases the benefit of noise. Jafarzadeh and Panda et al [16,17] have performed some research in the field of network-on-chip and photonic integrated circuits.…”
Section: Introductionmentioning
confidence: 99%
“…A single-phase multilevel inverter's performance enhancement can be obtained by the partial shading method, which can be done by cascading the multilevel inverter with the power network [31]. The generalized structure of the cascaded multilevel inverter is further modified with improved converter topology to reduce the total harmonic distortion employing solar photovoltaic applications [32][33][34][35][36][37][38].…”
Section: Introductionmentioning
confidence: 99%