A Novel High-Speed, Low-Power CNTFET-Based Inexact Full Adder Cell for Image Processing Application of Motion Detector

Mehrabani, Yavar Safaei; Mirzaee, Reza Faghih; Zareei, Zahra; Daryabari, Seyedeh Mohtaram

doi:10.1142/s0218126617500827

Cited by 27 publications

(25 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It can be measured using Equation , which is given as

PD = ((), Average power dissipation) \times ((), worst case delay) .

PDP of all the inexact FAs, proposed as well as existing, is listed in Column IV of Table . The proposed inexact FA shows reduction in PDP up to 89.2% as compared with existing inexact FA . This is achieved because of lesser number of switching nodes along with the lesser switching capacitance in the proposed inexact FA.…”

Section: Simulations and Discussionmentioning

confidence: 87%

“…Average power depends on total switched capacitance of the circuit. The proposed inexact FA achieves reduction in average power dissipation up to 93% as compared with the latest existing inexact FA . It is due to the reduction in capacitance of the switching nodes.…”

Section: Simulations and Discussionmentioning

confidence: 94%

“…So, to measure the stability of the proposed as well as existing inexact FA, the effect of voltage and temperature variations on leakage power dissipation is studied for all the FA under consideration in this paper. The existing inexact FA consumes large leakage power, which is in the order of μW, while all other inexact FA in this paper consume leakage power in the order of pW as shown in Table . So, to compare the effect of leakage power with temperature and voltage variations, we have used break graph which can be seen in Figures and , respectively.…”

Section: Simulations and Discussionmentioning

confidence: 99%

“…Result shows that proposed inexact FA consume 29.3‐pW average leakage power at 0.9‐V supply voltage which is the least leakage power dissipation among those compared in this paper. The reduction in leakage power is many fold as compared with the latest existing inexact FA . As the inexact FAs consume very large leakage power for input data “000” and “100” as shown in Table , so its average leakage power is in the order of μW as can be seen in Table .…”

Section: Simulations and Discussionmentioning

confidence: 99%

“…The reduction in leakage power is many fold as compared with the latest existing inexact FA . As the inexact FAs consume very large leakage power for input data “000” and “100” as shown in Table , so its average leakage power is in the order of μW as can be seen in Table . The reduction in leakage power in the proposed inexact FA is totally attributed to the approximation and simplification of the proposed inexact circuit which in turns reduces the number of transistors along with the total switched capacitance of the circuit.…”

Section: Simulations and Discussionmentioning

confidence: 99%

See 4 more Smart Citations

A low leakage TG‐CNTFET–based inexact full adder for low power image processing applications

Goyal¹,

Ubhi

Raj

2019

Circuit Theory & Apps

View full text Add to dashboard Cite

Summary This paper presents a highly stable, low leakage inexact full adder (FA) which is based on top gate carbon nanotube field effect transistors (TG‐CNTFET) for motion detector applications. Inexact arithmetic circuits are highly accepted in low power multimedia applications. Circuit level metrics, ie, average power, propagation delay, power‐delay product (PDP), and leakage power dissipation as well as application level metric such as peak signal to noise ratio (PSNR) are considered to compare the performance of proposed inexact FA. All the simulations are performed using HSPICE tool with Stanford 32‐nm TG‐CNTFET model. The operating frequency used for simulation is 1‐Ghz with 0.9‐V supply voltage. Proposed inexact FA successfully achieve manifold reduction in leakage power as well as consume 89.2% lesser energy as compared with latest existing inexact FA while having other parameters in acceptable range. Simulations using MATLAB show satisfactory image quality and PSNR value for motion detection applications. The effect of variations in voltage and temperature on leakage power is also presented which confirms stability of the proposed circuit.

show abstract

“…It can be measured using Equation , which is given as

PD = ((), Average power dissipation) \times ((), worst case delay) .

Section: Simulations and Discussionmentioning

confidence: 87%

Section: Simulations and Discussionmentioning

confidence: 94%

Section: Simulations and Discussionmentioning

confidence: 99%

Section: Simulations and Discussionmentioning

confidence: 99%

Section: Simulations and Discussionmentioning

confidence: 99%

See 3 more Smart Citations

A low leakage TG‐CNTFET–based inexact full adder for low power image processing applications

Goyal¹,

Ubhi

Raj

2019

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

Design and analysis of CNTFET based 10T SRAM for high performance at nanoscale

Kumar

Ubhi

2019

Circuit Theory & Apps

View full text Add to dashboard Cite

Summary The proposed 10T SRAM cell design is implemented for different CNTFET parameters like pitch, number of tubes, chirality, dielectric materials, and flatband voltage to analyze its effect on various performance parameters. The channel gate width, average read, and write power increase, but leakage power, read delay, and write delay decrease with the increase in pitch of CNTFET, whereas all these parameters are directly proportional to the number of tubes. Chirality alteration shows inverse effect on threshold voltage, read delay, and write delay although other parameters are directly related to it. The performance parameters are evaluated for various dielectric materials, and HfO2 gives the best results for low power and high‐speed applications. Analysis of flatband voltage on proposed 10T SRAM is performed by keeping flatband voltage constant for n‐CNTFET and varied for p‐CNTFET. Extensive analysis has been done to scrutinize the sharing of powers and delay of 10T SRAM because of variations in supply voltage and temperature. The supply voltage sweeps for a range between 0.6 and 1.2 V, and range of temperature variation is considered from −27 to 127°C. The stability of the proposed SRAM cell is calculated using N‐curve method to find voltage and current information. The CNTFET based 10T SRAM cell depicts that it persists supply voltage and temperature variation significantly superior than CMOS.

show abstract