A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme

Seogjun, Lee; Kim, Beomsup; Lee, Kwyro

doi:10.1109/4.551926

Cited by 144 publications

(25 citation statements)

References 4 publications

(4 reference statements)

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“…When the order is decided, how to reduce the delay time is the key point for high oscillator frequency. An interesting method is proposed [15]. It is called negative skewed delay cell.…”

Section: The Sscg Circuit Architecture In This Workmentioning

confidence: 99%

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A small area fully integrated spread-spectrum clock generator with high EMI-reduction for SATA-3.0 applications

Chiueh

Juang

et al. 2010

2010 53rd IEEE International Midwest Symposium on Circuits and Systems

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In this paper, a small area spread-spectrum clock generator (SSCG) with high EMI reduction for SATA-3.0 is presented. Conventional methods use inductor-capacitance (LC) tank to fulfill the high frequency requirement for SATA-3.0. However, the monolithic inductors always occupy a large area, and required precisely characteristic for different fabrication processes. This research propose a SSCG using a ring voltagecontrolled oscillators (Ring-VCO) at 6GHz operating frequency; By using the proposed Ring-VCO, the active area of SSCG is 65% of comparable LC tank implementations, and Ring-VCO is much easier to characterized for any CMOS process. In addition, a multi-stage-noise-shaping (MASH) delta-sigma modulator (ΔΣ modulator) is used to reduce fractional spurs and quantization error for high EMI reduction. The chip is designed in TSMC 0.18um 1P6M CMOS process with active area of 500um×300um, and the simulation results consumes 60.43mW with 1.8V supply. The peak-to-peak jitter at 6GHz output of non spread-spectrum is 6.16ps, and the EMI reduction is 22.49dB with 5000ppm down spread to 5.97GHz.

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“…When the order is decided, how to reduce the delay time is the key point for high oscillator frequency. An interesting method is proposed [15]. It is called negative skewed delay cell.…”

Section: The Sscg Circuit Architecture In This Workmentioning

confidence: 99%

“…A lot of works try to improve Ring-VCO speed. An efficient method is proposed [15]. It is called negative skewed delay cell.…”

Section: Introductionmentioning

confidence: 99%

A small area fully integrated spread-spectrum clock generator with high EMI-reduction for SATA-3.0 applications

Chiueh

Juang

et al. 2010

2010 53rd IEEE International Midwest Symposium on Circuits and Systems

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“…The In order to achieve a high operating frequency, the ring oscillator employed a dynamic loading technique with negative skew [11]. The clock input turns on Mp 1 before low-to-high output (out) transitions and turns off the PMOS before high-to-low output (out) transitions.…”

Section: Circuit Implementationmentioning

confidence: 99%

“…The clock input turns on Mp 1 before low-to-high output (out) transitions and turns off the PMOS before high-to-low output (out) transitions. It speeds up the [11]. Another way to maximize the oscillating frequency is that the transconductance to drain capacitance ratio (g m /C T ) of the NMOS input pair (M n1 , M n4 ) is maximized to achieve a high operating frequency with low power dissipation.…”

Section: Circuit Implementationmentioning

confidence: 99%

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A 1.8-V 2.4-GHz monolithic CMOS inductor-less frequency synthesizer for Bluetooth application

Wong¹

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Bluetooth is a new wireless standard that uses short-range radio links to replace the cables connecting portable and/or fixed electronic devices. The standard defines a uniform structure for a wide range of devices to communicate with each other. The goal of Bluetooth transceivers is to achieve robustness, low complexity, low power and low cost. Conventional monolithic frequency synthesizer is difficult to fulfil the Bluetooth specifications. Traditional designs usually generate a 2.4-GHz signal using LC-oscillators with on-chip spiral inductors. These inductors have low quality factors, occupy a large chip area, and are quite sensitive to process variation, which degrade the performance in terms of cost, power and production yield. 102 103 103 105 106 108 110 112 Chapter 6 Conclusion 113

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Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks

Elissati

Rieubon²,

Yahya

et al. 2012

IFIP Advances in Information and Communication Technology

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Abstract.A high-speed multi-phase oscillator based on self-timed ring is proposed. Self-timed rings (STR) are promising approach for designing highspeed serial links and clock generators. Indeed, the architecture of STR allows us to achieve high frequencies with multiphase outputs and their oscillation frequency is not only depending on the number of stages but also on the initial state of the ring. Moreover, this architecture allows us 3 dB phase noise reduction when, while keeping the same frequency, when the stage number is doubled. In this chapter, we propose a method to design STR able to generate high-speed multi-phase outputs and we suggest a design flow for designing low-phase noise self-timed ring oscillators. A test chip has been designed and fabricated in STMicroelectonics CMOS65nm technology to verify the theoretical claims and validate the simulation results.

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A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme

Cited by 144 publications

References 4 publications

A small area fully integrated spread-spectrum clock generator with high EMI-reduction for SATA-3.0 applications

A small area fully integrated spread-spectrum clock generator with high EMI-reduction for SATA-3.0 applications

A 1.8-V 2.4-GHz monolithic CMOS inductor-less frequency synthesizer for Bluetooth application

Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks

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