A Novel Simplified Log-Likelihood Ratio for Soft-Output Demapping of CMMB

Sun, Xiangran; Zeng, Zhibin

doi:10.1007/978-3-642-22456-0_51

Cited by 3 publications

(1 citation statement)

References 5 publications

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“…Note that this soft demapping approach has an increasing computational complexity with constellation size and transmit antennas therefore we further simplify the algorithm to maintain approximately the same complexity according to [17]. Consider a QAM constellation with d n as half the distance between the partition boundaries relative to b n for n > 1 (see appendix).…”

Section: Zero Forcing Receivermentioning

confidence: 99%

Performance analysis and soft demapping for coded MIMO-OFDM systems

Abdullahi

Xiao

2016

2016 International Symposium on Wireless Communication Systems (ISWCS)

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Abstract-Multiple input multiple output-Orthogonal frequency division multiplexing (MIMO-OFDM) is a viable solution for providing high data rate services in harsh channel environments. The optimum receivers for them are those based on the maximum likelihood criterion. However, they have a prohibitive complexity especially when channel dimensions are high and coding is employed. Zero Forcing (ZF) and Linear Minimum Mean Square Error (MMSE) receivers on the other hand provide practicable and low complexity solutions for detection, but require soft demappers to deduce the soft bits information contained in each of the received symbols. In this work, we present the ZF and MMSE receiver analysis of a bit interleaved and coded MIMO-OFDM system and propose a soft output demapper based on MMSE equalizer output to demap the information needed for viterbi decoding. A comparison of the proposed soft demapper with conventional soft demappers in literature show a significant performance improvement. We also noticed that it is more advantageous to apply the proposed demapper on a MIMO-OFDM system employing higher modulation schemes.

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Section: Zero Forcing Receivermentioning

confidence: 99%

Performance analysis and soft demapping for coded MIMO-OFDM systems

Abdullahi

Xiao

2016

2016 International Symposium on Wireless Communication Systems (ISWCS)

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A Literature Survey on Algorithms and Hardware Architectures of Max-Log-MAP Demapping

Rizk

Baghdadi

Jézéquel

2021

J CIRCUIT SYST COMP

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Emergent wireless communication standards, which are employed in different transmission environments, support various modulation schemes. High-order constellations are targeted to achieve high bandwidth efficiency. However, the complexity of the symbol-by-symbol Maximum A Posteriori (MAP) algorithm increases dramatically for these high-order modulation schemes. In order to reduce the hardware complexity, the suboptimal Max-Log-MAP, which is the direct transformation of the MAP algorithm into logarithmic domain, is alternatively implemented. In the literature, a great deal of research effort has been invested into Max-Log-MAP demapping. Several simplifications are presented to meet with specific constellations. In addition, the hardware implementations dedicated for Max-Log-MAP demapping vary greatly in terms of design choices, supported flexibility and performance criteria, making them a challenge to compare. This paper explores the published Max-Log-MAP algorithm simplifications and existing hardware demapper designs and presents an extensive review of the current literature. In-depth comparisons are drawn amongst the designs and different key performance characteristics are described, namely, achieved throughput, hardware resource requirements and flexibility. This survey should facilitate fair comparisons of future designs, as well as opportunities for improving the design of Max-Log-MAP demappers.

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A high throughput architecture for a low complexity soft-output demapping algorithm

2015

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Abstract. Iterative channel decoders such as Turbo-Code and LDPC decoders show exceptional performance and therefore they are a part of many wireless communication receivers nowadays. These decoders require a soft input, i.e., the logarithmic likelihood ratio (LLR) of the received bits with a typical quantization of 4 to 6 bits. For computing the LLR values from a received complex symbol, a soft demapper is employed in the receiver. The implementation cost of traditional soft-output demapping methods is relatively large in high order modulation systems, and therefore low complexity demapping algorithms are indispensable in low power receivers. In the presence of multiple wireless communication standards where each standard defines multiple modulation schemes, there is a need to have an efficient demapper architecture covering all the flexibility requirements of these standards. Another challenge associated with hardware implementation of the demapper is to achieve a very high throughput in double iterative systems, for instance, MIMO and Code-Aided Synchronization. In this paper, we present a comprehensive communication and hardware performance evaluation of low complexity soft-output demapping algorithms to select the best algorithm for implementation. The main goal of this work is to design a high throughput, flexible, and area efficient architecture. We describe architectures to execute the investigated algorithms. We implement these architectures on a FPGA device to evaluate their hardware performance. The work has resulted in a hardware architecture based on the figured out best low complexity algorithm delivering a high throughput of 166 Msymbols/second for Gray mapped 16-QAM modulation on Virtex-5. This efficient architecture occupies only 127 slice registers, 248 slice LUTs and 2 DSP48Es.

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A Novel Simplified Log-Likelihood Ratio for Soft-Output Demapping of CMMB

Cited by 3 publications

References 5 publications

Performance analysis and soft demapping for coded MIMO-OFDM systems

Performance analysis and soft demapping for coded MIMO-OFDM systems

A Literature Survey on Algorithms and Hardware Architectures of Max-Log-MAP Demapping

A high throughput architecture for a low complexity soft-output demapping algorithm

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