A novel structure for portable digitally controlled oscillator

Jong, Jin-Jer; Lee, Chen‐Yi

doi:10.1109/iscas.2001.921845

Cited by 7 publications

References 4 publications

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A crystal-based digital ring oscillator

Abdollahi

Fakhraei

Bakkaloglu

et al.

Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798)

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A 0.16 m W, 2.3Volt multi-channel digitally controlled oscillaior (MICO) core is designed in a 0.6 micron CMOS process and its prototype design is mapped on an Altera FPGA that can be used for clock recovery applications. This architecture is suitable for digital wireless and cable hwnsceivers that use different bands for transmit and receive modes. As crysial-based-delay cells control its dominant propagation delay, we have obtained a reducedphase-noise in comparison to recently published analog-based DCOs.

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A crystal-based digital ring oscillator

Abdollahi

Fakhraei

Bakkaloglu

et al.

Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798)

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A Scalable DCO Design for Portable ADPLL Designs

Wu¹,

Wang²,

Wey³

et al.

2005 IEEE International Symposium on Circuits and Systems

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Abstract-A novel Digital Controlled Oscillator (DCO) design methodology is presented in this paper. The new design methodology includes a scalable DCO architecture and the developed design flow. With precise analysis in early stage, the design effort of DCO can be reduced significantly. The proposed DCO architecture has the characteristics of, high resolution, flexible operating range, and easy design. The design is suitable for high performance clock generator in System on a Chip (SoC) application.

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An all-digital phase-locked loop for high-speed clock generation

Chung

Lee

2003

IEEE J. Solid-State Circuits

182

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Abstract-An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented in this brief. The proposed ADPLL architecture uses both a digital control mechanism and a ring oscillator and, hence, can be implemented with standard cells. The ADPLL implemented in a 0.3-m one-poly-four-metal CMOS process can operate from 45 to 510 MHz and achieve worst case frequency acquisition in 46 reference clock cycles. The power dissipation of the ADPLL is 100 mW (at 500 MHz) with a 3.3-V power supply. From chip measurement results, the -jitter of the output clock is 70 ps, and the root-mean-square jitter of the output clock is 22 ps. A systematic way to design the ADPLL with the specified standard cell library is also presented in this brief. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for system-on-chip applications.Index Terms-All-digital phase-locked loop (ADPLL), clock generator, frequency synthesizer, HDL, low jitter.

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A novel structure for portable digitally controlled oscillator

Cited by 7 publications

References 4 publications

A crystal-based digital ring oscillator

A crystal-based digital ring oscillator

A Scalable DCO Design for Portable ADPLL Designs

An all-digital phase-locked loop for high-speed clock generation

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