A novel subthreshold slope technique for the extraction of the buried-oxide interface trap density in the fully depleted SOI MOSFET

Lun, Zhiyuan; Ang, Diing Shenp; Ling, C.H.

doi:10.1109/55.852967

Cited by 26 publications

(23 citation statements)

References 12 publications

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“…In some of these reports analytical models have been used for extracting the Dit in FD-SOI MOSFETs [10], [11]. Also in the field of GAA Si nanowire FETs analytical models have been used with [12], [13] or without [14] the aid of numerical simulation tools.…”

Section: Ilialmentioning

confidence: 99%

Interface trap density estimation in FinFETs from the subthreshold current

Schmitz

Kaleli

Kuipers

et al. 2016

2016 International Conference on Microelectronic Test Structures (ICMTS)

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In this work we present a measurement approach to determine the interface trap density in FinFETs as a function of their energy. It is hased on the precise determination of the gate voltage dependent ideality factor of the suhthreshold current in this device. The required measurement accuracy for temperature, drain current and transconductance is derived, and we propose an implementation for wafer-level device measurement on contemporary test set-ups. Exemplary interface trap distributions are shown as obtained from two FinFET device technologies, featuring the commonly observed bathtub shape.

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Section: Ilialmentioning

confidence: 99%

Interface trap density estimation in FinFETs from the subthreshold current

Schmitz

Kaleli

Kuipers

et al. 2016

2016 International Conference on Microelectronic Test Structures (ICMTS)

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“…Our approach for estimation of D IF,IB (E IT ) dependences from STS measurements is based mainly on the theory and calculations presented in the previous publications (see refs. [9][10][11]15] and references therein). Where possible, we will refer to the previously published equations to avoid lengthy and cumbersome expressions related to the complexity of the system under consideration.…”

Section: Short Review Of the Previous Studiesmentioning

confidence: 99%

“…First attempts to estimate D IB in MOSFET SOI devices based on the STS method was presented in ref. [9]. Later this method was developed in several works for MOSFET SOI devices (see, e.g., ref.…”

Section: Introductionmentioning

confidence: 99%

Characterization of Ultrathin Fully Depleted Silicon‐on‐Insulator Devices Using Subthreshold Slope Method

Mchedlidze

Erben

2020

Physica Status Solidi (a)

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The subthreshold current-voltage (subthreshold slope) characteristic of a fully depleted silicon-on-insulator high-k dielectric-metal gate field-effect transistor is applied for evaluation of the interface traps located at both the front and back channels. The proposed characterization method allows an estimation of averaged trap densities separately for the front and back interfaces of the channel. Performing subthreshold slope measurements at several temperatures allows the extraction of the energy distributions of the interface trap densities for both interfaces and obtaining essential characteristics of the stack.

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“…Therefore, a dual-gate (DG) voltage-sweep technique has been utilized to characterize the buried density of interface traps (D itB ) for FD-SOI involving sweeping both channels in sub-threshold region, thus an average back channel D itB can be derived by neglecting the D itF . 18 However, ignoring the D itF introduces unknown errors and an average D itB leaves much information unexamined. D itB and D itF should be functions of the surface energy in general.…”

mentioning

confidence: 99%

Extraction of Front and Buried Oxide Interface Trap Densities in Fully Depleted Silicon-On-Insulator Metal-Oxide-Semiconductor Field-Effect Transistor

Cheng

Yeung

2013

ECS Solid State Letters

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In this letter, a method is proposed and demonstrated for the first time to characterize and decouple the interface traps of both the frontand back channels of fully-depleted silicon-on-insulator (FD-SOI) metal-oxide-semiconductor field-effect transistor (MOSFET). We report the procedure and the underlying theory that allows the extraction of the energy profiles of the densities of the interface traps (D it ).This technique will be very useful for evaluating the interface qualities of future FD-SOI transistors.The fully-depleted silicon on insulator (FD-SOI) ultra-thin body UTBSOI MOSFET 1-3 is gaining new attention as an alternative technology to FinFET 4 for ultra-low power and mobile applications because of its outstanding electrostatics, low device variability due to excellent suppression of the short channel effect (SCE) with undoped channel and ultra-thin body. 5,6 UTB structure also offers great compatibility with mainstream planar CMOS for high density integration. 7,8 The performance of these FD-SOI devices are inevitably influenced by the interface traps of buried oxide, in addition to those of the front oxide, as they would degrade the sub-threshold swing, transconductance and device uniformity as the film thicknesses are scaled down. 9 Thus, a simple and reliable approach for D it extraction for both the front and back interfaces simultaneously is highly desired. The most commonly used technique for characterizing the D it , i.e., the charge pumping (CP) method, requires a body contact and/or with additional optical assistance as well as a gated-diode-like device 10-13 to supply the majority carrier, cannot be applied to future FD-SOI technologies as they do not provide body contacts. Nevertheless, conductance method only reflects mixing result of front-and back density of interface state instead of their individual contribution. Besides, conventional capacitance-voltage (C-V) method 14,15 is not appropriate for FD-SOI nowadays because of the large gate leakage current at low frequencies and the high series resistance at high frequencies. Therefore, DC current-voltage based technique is the most attractive. One may apply the sub-threshold technique by accumulating one channel while sweeping the gate bias of the opposite channel to evaluate the D it , and it works well for a relatively thick film. 16 However, for the very thin silicon film thicknesses, it is not possible to accumulate one channel while inverting the opposite channel without using high voltages that would damage the thin gate oxide due to the strong capacitive coupling of the two channels. 17 The back surface potential will always follow the front gate voltage, i.e., the volume inversion occurs. Therefore, a dual-gate (DG) voltage-sweep technique has been utilized to characterize the buried density of interface traps (D itB ) for FD-SOI involving sweeping both channels in sub-threshold region, thus an average back channel D itB can be derived by neglecting the D itF . 18 However, ignoring the D itF introduces unknown errors and an avera...

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A novel subthreshold slope technique for the extraction of the buried-oxide interface trap density in the fully depleted SOI MOSFET

Cited by 26 publications

References 12 publications

Interface trap density estimation in FinFETs from the subthreshold current

Interface trap density estimation in FinFETs from the subthreshold current

Characterization of Ultrathin Fully Depleted Silicon‐on‐Insulator Devices Using Subthreshold Slope Method

Extraction of Front and Buried Oxide Interface Trap Densities in Fully Depleted Silicon-On-Insulator Metal-Oxide-Semiconductor Field-Effect Transistor

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