A Physics Based Resistance Model of the Overlap Regions in LDD-MOSFETs

Gondro, E.; Schuler, F.; Klein, P.

doi:10.1007/978-3-7091-6827-1_67

Cited by 7 publications

(4 citation statements)

References 3 publications

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“…This is unlike the work described in [6] where the surface potential in junctions was neglected and thus derivation of the gate bias dependence of accumulation layer charges was oversimplified. R acc1 under the uniform gate oxide is evaluated by integration of the local resistivity along the lateral junction depletion region.…”

Section: Analytical Modelmentioning

confidence: 76%

Series resistance in vertical MOSFETs with reduced drain/source overlap capacitance

Tan

Hall

Buiu

et al. 2008

2008 9th International Conference on Ultimate Integration of Silicon

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In this work we investigate the series resistances in vertical MOSFETs incorporating the fillet local oxidation (FILOX) structure that serves to reduce the gate to drain/source overlap capacitances. The series resistances are modeled analytically and the important influencing factors, namely gate bias dependence and the asymmetric nature of the device, are identified. We extract by simulation, R d and R s from devices with different FILOX thicknesses, employing an impedance method often used in RF characterisation. We identify the trade-off whereby thickening the FILOX first causes an increase of the cut-off frequency f T , until the on-current I on becomes limited by increasing series resistances and f T therefore reduces. The results indicate a thickness of 40nm FILOX for maximum f T . We also investigate the influence of process conditions on low series resistances, namely time of rapid thermal annealing RTA and angle of implantation.

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Section: Analytical Modelmentioning

confidence: 76%

Series resistance in vertical MOSFETs with reduced drain/source overlap capacitance

Tan

Hall

Buiu

et al. 2008

2008 9th International Conference on Ultimate Integration of Silicon

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“…The advantage of our strategy is a physics-based welldefined separation of the inner transistor from parasitic effects (5,6).…”

Section: -1 -mentioning

confidence: 99%

When do we need non-quasistatic CMOS RF-models?

Gondro

Kowarik

Knoblinger

et al.

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

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“…However, this is a time-consuming procedure, and the accuracy of the results is doubtful. Instead, following our overall emphasis on analytic modeling, we employ a set of models [4], [5] describing all components of in a closed-form manner. The following equivalent model is used ( Fig.…”

Section: Additional Device Modelingmentioning

confidence: 99%

“…It is well known that electrical , estimated during the device parameter extraction, may be different from the physical (defined as the distance between the source and drain regions). We propose a capacitance-based formulation (5) and are overlap and fringing capacitances and is the channel width. Here, the constraint is the value of the overlap capacitance , usually, determined by the required ring oscillator speed.…”

Section: Constraint Back Propagationmentioning

confidence: 99%

Efficient generation of pre-silicon MOS model parameters for early circuit design

Orshansky¹,

Jiang

et al. 2001

IEEE J. Solid-State Circuits

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The technology development cycle continues to shrink, which very often requires evaluation of circuit design and technology choices using circuit simulators at the time when no real silicon is available. In this paper, we present an efficient methodology for generating pre-silicon device models for advanced CMOS processes. The methodology allows accurate prediction of the full MOS-characteristics for the future technologies combining a constraint back-propagation algorithm based upon a few critical specifications, physical models for the advanced device phenomena, and the empirical data from devices of an existing technology. The methodology has been tested on two CMOS production technologies. Good prediction results are achieved: for nMOS the rms error is 1%-2%, for pMOS it is 2%-4%. Index Terms-BSIM3, CMOS modeling, compact modeling. I. INTRODUCTION W ITH THE reduction of the technology development cycle, it becomes increasingly important to be able to predict the performance of the next-generation devices. The ability to do such a prediction would be useful both for early circuit design efforts and technology development. The circuit designers would be provided with SPICE models long before any real silicon is available for model extraction, enabling them to evaluate their circuits under the realistic conditions. Technology groups could use it as a tool to evaluate the device being developed, consider the alternatives, and optimize the device performance for the number of targets and design choices. The attempts at pre-silicon SPICE model generation has previously relied on an extremely time-consuming process and device simulation which is also not very accurate because of lack of good high-field mobility models. Here we propose an efficient methodology that is based on a compact BSIM3v3 device model. Accuracy of results is ensured by the introduction of the constraint back-propagation method. First, accurate physical MOS models are needed. We adopt BSIM3v3 as our main predictive tool, because it is a standard compact model that is well tested and widely used in the industry [1]. It is a physics-based model that accurately models many advanced MOS phenomena. However, we found that some effects that become important with device scaling are not yet included into most commercially available versions of the model, and thus require additional external modeling. These are quantization of inversion-layer charge and velocity overshoot.

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A Physics Based Resistance Model of the Overlap Regions in LDD-MOSFETs

Abstract: A new resistance model for lightly doped source/drain regions featuring a nonlinear gate voltage dependence has been implemented in the Bsim3 v3 model. This is achieved by separating the LDS(D) resistance into a voltage dependent accumulation and a spreading part.

Cited by 7 publications

References 3 publications

Series resistance in vertical MOSFETs with reduced drain/source overlap capacitance

Series resistance in vertical MOSFETs with reduced drain/source overlap capacitance

When do we need non-quasistatic CMOS RF-models?

Efficient generation of pre-silicon MOS model parameters for early circuit design

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