A power efficient 3-Gbits/s 1.8V PMOS-based LVDS output driver

Marar, Hazem W.; Abugharbieh, Khaldoon; Al-Tamimi, Abdel-Karim

doi:10.1109/icecs.2012.6463756

Cited by 6 publications

(6 citation statements)

References 4 publications

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“…Recently, the LVDS drivers achieve a higher data rate with an advanced process and technology. Hazem W. Marar' s paper lists a LVDS driver with a data rate of 3Gbps by adding a pre-driver in 0.18-μm CMOS process [9]. By using a positive-feedback and impedance matching technique in a 2.5V/1.2VSiGe BiCMOS process, the data rate of LVDS driver can achieve 10Gbps in Khaldoon Abugharbieh' s paper [10].…”

Section: Simulation and Measurement Resultsmentioning

confidence: 98%

A High-Speed LVDS Driver Design in 0.35-μm CMOS Technology

Wang

Guo

Peng

2015

Proceedings of the Second International Conference on Mechatronics and Automatic Control

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With the development of new technologies, the operating frequencies on chip are increasing at a faster rate, such as computational methods, utilization of high-frequency clocks, digital circuits, etc. The process-technology-independent I/O standard, low-voltage differential signaling (LVDS), is basically developed for low-voltage, low-power, low-noise, and high-speed I/O interfaces. Low power is owing to the use of very small differential swing, while low noise is owing to essential nature of the differential circuits. Based upon ANSI TIA/EIA-644 LVDS standard, this paper presents a low-voltage and high-speed LVDS driver. A Common-mode feedback (CMFB) and a pull-up/down circuits were suggested as carried out by a standard 0.35-μm complementary metal oxide semiconductor (CMOS) process with a die area of 0.115 mm 2 . The measured results present that the driver works well at 1.5 Gbps, and the static current is less than 11.5 mA under 3.3 V. Keywords CMFB · High speed · LVDS · Rise/fall time IntroductionLVDS driver plays an important role in point-to-point communication with more and more data stream quantity and increasing data rate, as microprocessor main board, high-speed ADC/DAC, optical transmission links, etc [1].While the scaled CMOS technology continues to enhance the speed of operating speed but the I/O interface still confines the rate of data process, so the LVDS I/O interface becomes necessary. The point-to-point LVDS interface is shown in Fig. 110.1. Saving by a different scheme for transmission, termination, and a low-voltage swing, LVDS completes significant power [2]. LVDS standards put relatively stringent requirement on the tolerance influencing the output levels, gaining interesting design issues if low-cost solutions with neither external components nor trimming procedures are required. In the meantime, the very large tolerance for the common-mode

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Section: Simulation and Measurement Resultsmentioning

confidence: 98%

A High-Speed LVDS Driver Design in 0.35-μm CMOS Technology

Wang

Guo

Peng

2015

Proceedings of the Second International Conference on Mechatronics and Automatic Control

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“…It employs differential data transmission and the receiver is configured as a switched-polarity signal generator. The receiver is composed of a pre-stage common mode voltage (Vcm) shifter and a rail-to-rail comparator (COMP), while the transmitter includes a CMOS H-bridge output driver with a common mode feedback (CMFB) circuit, a high- In general, the architecture of LVDS drivers is divided into fully-differential NMOS-only style [12], fully-differential PMOS-only style [13] and complementary MOS style [14][15][16]. As shown in Figure 2, all configurations consist of four MOS switches arranged in an H-bridge structure.…”

Section: Architecture Designmentioning

confidence: 99%

“…In addition, the wide common mode input of LVDS makes its devices easily interoperable with other differential signaling technologies [9][10][11]. In general, the architecture of LVDS drivers is divided into fully-differential NMOS-only style [12], fully-differential PMOS-only style [13] and complementary MOS style [14][15][16]. As shown in Figure 2, all configurations consist of four MOS switches arranged in an H-bridge structure.…”

Section: Introductionmentioning

confidence: 99%

A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

et al. 2019

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This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 ps@2.5 Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.

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“…At the same time, the voltage‐mode core is operated by the PD through replica action . The PD is a scaled‐down replica of the OD, generating the same v DS across its transconductors (M1PD and M2PD) as that of the OD's transconductors.…”

Section: Design Descriptionmentioning

confidence: 99%

“…A similar approach in Ref. uses passive resistors in series with source‐follower output stages, that is, series combination of 1/gm from the source follower and the passive resistors. However, to achieve the required matched differential termination, it also ends up consuming twice the amount of power consumption; that is, it becomes almost equivalent to using a passive class II termination.…”

Section: Introductionmentioning

confidence: 99%

A configurable 2‐Gbps LVDS transceiver in 150‐nm CMOS with pre‐emphasis, equalization, and slew rate control

Jawed

Ali

Khan

et al. 2016

Circuit Theory & Apps

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Summary A configurable full‐duplex low‐voltage differential signaling transceiver is presented, which can be configured to operate either for smaller differential channels (a few inches of striplines) or for longer channels (10 m of twisted pair cables). The configurability is embedded in the form of functionalities like pre‐emphasis, equalization, and slew rate control within the transceiver. The transmitter employs a hybrid voltage–current‐mode driver, which due to replica action, achieves a high‐impedance current‐mode signal dispatch and at the same time provides a matched impedance at the near end for improved intersymbol interference. The transmitter achieves slew rate control through a band‐limited pre‐driver, while the pre‐emphasis is achieved through a capacitive feed‐forward. The receiver employs a large‐input common‐mode first stage enclosed in a common‐mode control loop that enables its first stage to also act like a domain shifter (VDDIO‐to‐VDDCORE) reducing the overall power consumption. The equalization in the receiver is implemented by using carefully sized active inductive loads inside the receiver. The transceiver is designed and fabricated in 150‐nm complementary metal–oxide–semiconductor, sharing the space with a larger die, occupying an area of 400 × 400μm. The measurement results demonstrate that the transceiver is operating at 2 Gbps both for a 4‐in microstrip and a 10‐m twisted pair CAT6 cable with 30 and 180 ps of total jitter, respectively. The built‐in impedance calibrator minimizes the spread in the on‐die termination at the near end provided by the transmitter‐minimizing bit error rate across process, voltage, and temperature corners. The transmitter consumes a total power of 17 mW operating at 2 Gbps, that is, 8.5 pJ/bit of energy consumption; the receiver consumes a total power of 3.5 mW while driving a load of 5 pF at 2 Gbps. Copyright © 2016 John Wiley & Sons, Ltd.

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A power efficient 3-Gbits/s 1.8V PMOS-based LVDS output driver

Cited by 6 publications

References 4 publications

A High-Speed LVDS Driver Design in 0.35-μm CMOS Technology

A High-Speed LVDS Driver Design in 0.35-μm CMOS Technology

A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

A configurable 2‐Gbps LVDS transceiver in 150‐nm CMOS with pre‐emphasis, equalization, and slew rate control

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