A Predictive Model for IC Self-Heating Based on Effective Medium and Image Charge Theories and Its Implications for Interconnect and Transistor Reliability

Ahn, Woojin; Zhang, Haojun; Shen, Tian; Christiansen, C.; Justison, Patrick; Shin, Sanghoon; Alam, Muhammad Ashraful

doi:10.1109/ted.2017.2725742

Cited by 31 publications

(35 citation statements)

References 34 publications

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“…Fig. 8 shows a comparison between the maximum temperature change on each metal layer estimated with [18] and simulated with the primary heat source at the center, at the corner and at the center and the corner (Fig. 3, 5 and 7).…”

Section: Fem Model Structurementioning

confidence: 99%

Numerical Simulation of the Temperature on the Metallization of an Integrated Circuit and its Impact on Interconnect Lifetime

Nunes

Bohorquez²,

Orio³

2020

JICS

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This paper demonstrates a finite element model to investigate the temperature change of the interconnects of an integrated circuit due to the power dissipation of the transistors in the substrate. The temperature of the local interconnect is more significantly affected, exhibiting an increase of 49 K and 34 K, for the Metal 1 and Metal 2, respectively. We discuss the impact of the temperature increase in the electromigration and, as a consequence in the lifetime of an operational amplifier, which demonstrates the importance of considering the metallization temperature distribution in the design stage.

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Section: Fem Model Structurementioning

confidence: 99%

Numerical Simulation of the Temperature on the Metallization of an Integrated Circuit and its Impact on Interconnect Lifetime

Nunes

Bohorquez²,

Orio³

2020

JICS

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“…All the available models can reflect the evolution and state of the art for interconnect modeling [26] [27]. However, the modeling analysis in complicated circuit has not been studied, which is the next spot in future.…”

Section: Trend Of Interconnect Modelingmentioning

confidence: 99%

Review of the Global Trend of Interconnect Reliability for Integrated Circuit

Lin¹,

Wu²,

Jia³

2018

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Interconnect reliability has been regarded as a discipline that must be seriously taken into account from the early design phase of integrated circuit (IC). In order to study the status and trend of the interconnect reliability, a comprehensive review of the published literatures is carried out. This can depict the global trend of ICs' interconnect reliability and help the new entrants to understand the present situation of this area.

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“…Using this method increases the electric field across the gate oxide (between the channel and the gate oxide). It also causes the occurrence of degradation phenomena such as Negative Bias Temperature Instability (NBTI), Positive Bias Temperature Instability (PBTI), Time-Dependent Dielectric Breakdown (TDDB) and Hot Carrier Injection (HCI) [1,2]. These degradation mechanisms make it too hard to meet the circuit lifetime specification using deep nanometer scaled dimensions.…”

Section: Introductionmentioning

confidence: 99%

“…These degradation mechanisms make it too hard to meet the circuit lifetime specification using deep nanometer scaled dimensions. Additionally, the NBTI and PBTI are the critical factors causing degradation bellow 2 nm oxide thickness [2]. Since FinFET devices are not doped, the current density is very high at the channel-gate-oxide interface which causes acceleration of the charge carrier to interface into the gate oxide from the channel and it further increases with the stress [3].…”

Section: Introductionmentioning

confidence: 99%

A Reactive and On-Chip Sensor Circuit for NBTI and PBTI Resilient SRAM Design

Yadav¹,

Kim²,

Alashi³

et al. 2020

Electronics

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Process Variation (PV), Bias Temperature Instability (BTI) and Time-Dependent Dielectric Breakdown (TDDB) are the critical factors that affect the reliability of semiconductor chip design. They cause the system to be unstable and increase the soft error rate. In this paper, a compact on-chip degradation technique using runtime leakage current monitoring has been proposed. The proposed sensor-based adaptive technique compensates for the variation due to PV and aging using the body-bias-voltage-generator circuit. Simulation experiments for three and ten-year stress have been performed. Simulation results proved the superiority of the proposed sensor which provides 33% (up to 0.75 V) more output voltage and 98% sensitivity at 1 V supply voltage compared to the state-of-the-art sensor. The proposed technique mitigates up to 80% PV and BTI effects in SRAM compared to the state-of-the-art techniques.

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A Predictive Model for IC Self-Heating Based on Effective Medium and Image Charge Theories and Its Implications for Interconnect and Transistor Reliability

Cited by 31 publications

References 34 publications

Numerical Simulation of the Temperature on the Metallization of an Integrated Circuit and its Impact on Interconnect Lifetime

Numerical Simulation of the Temperature on the Metallization of an Integrated Circuit and its Impact on Interconnect Lifetime

Review of the Global Trend of Interconnect Reliability for Integrated Circuit

A Reactive and On-Chip Sensor Circuit for NBTI and PBTI Resilient SRAM Design

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