A Real-Time Spike Sorting System Using Parallel OSort Clustering

Valencia, Daniel; Alimohammad, Amirhossein

doi:10.1109/tbcas.2019.2947618

Cited by 30 publications

(44 citation statements)

References 32 publications

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“…Content may change prior to final publication. [18] POSort [28] Yang [27] Dragas [36] Valencia [37] Sungjin Oh [38] Schäffer [39] This work Year 2018 2019 2017 2015 2019 2017 2020 2020 FPGA Xilinx Kintex-7 Xilinx Virtex-6 Altera Cyclone III Xilinx Virtex-6 Xilinx Artix-7 Xilinx Spartan-6 + PC Xilinx Zinq Ultrascale+ Xilinx Zinq-7000 Input Channels 128 1 32 90 1 1 128 4096 Output Channels 8 0 0 0 0 0 0 16 Sampling [KHz] 32 .5 24 20 20 24 50 20 18 Detection yes yes TEO -TEO 2T TEO DT Feature no no DWT --ZCF -…”

Section: Discussionmentioning

confidence: 99%

“…Two main different kinds of approaches can be used. A first method runs a data-stream clustering algorithm, as in [24] and in [28]. A second possibility is, otherwise, to approximate the cluster centers considering a reduced recording time during the experiment, and consequently a limited number of spikes, and then use such centers to classify the incoming spikes during the remaining experiment duration, as in [23].…”

Section: Target Spike Sorting Pipelinementioning

confidence: 99%

“…Even considering 16 bits of resolution like in [18], instead of 12 bits, our memory would increase to 1.23 Kb only. The Parallel OSort algorithm (POSort), presented in [28], is prototyped on both the Xilinx Spartan-6 and the Xilinx Virtex-6 devices. Table 8 reports the Virtex-6 single channel implementation features, since it is the best version, in terms of accuracy and latency, between the fully documented ones shown in [28].…”

Section: ) Spike Window Centering Explorationmentioning

confidence: 99%

“…The Parallel OSort algorithm (POSort), presented in [28], is prototyped on both the Xilinx Spartan-6 and the Xilinx Virtex-6 devices. Table 8 reports the Virtex-6 single channel implementation features, since it is the best version, in terms of accuracy and latency, between the fully documented ones shown in [28]. However, the POSort can handle up to 64 and 128 channels if hosted by high-end FPGAs like those in the Virtex and Kintex families.…”

Section: ) Spike Window Centering Explorationmentioning

confidence: 99%

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ZyON: Enabling Spike Sorting on APSoC-Based Signal Processors for High-Density Microelectrode Arrays

2020

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Multi-Electrode Arrays and High-Density Multi-Electrode Arrays of sensors are a key instrument in neuroscience research. Such devices are evolving to provide ever-increasing temporal and spatial resolution, paving the way to unprecedented results when it comes to understanding the behaviour of neuronal networks and interacting with them. However, in some experimental cases, in-place lowlatency processing of the sensor data acquired by the arrays is required. This poses the need for highperformance embedded computing platforms capable of processing in real-time the stream of samples produced by the acquisition front-end to extract higher-level information. Previous work has demonstrated that Field-Programmable Gate Array and All-Programmable System-On-Chip devices are suitable target technology for the implementation of real-time processors of High-Density Multi-Electrode Arrays data. However, approaches available in literature can process a limited number of channels or are designed to execute only the first steps of the neural signal processing chain. In this work, we propose an All-Programmable System-On-Chip based implementation capable of sorting neural spikes acquired by the sensors, to associate the shape of each spike to a specific firing neuron. Our system, implemented on a Xilinx Z7020 All-Programmable System-On-Chip is capable of executing on-line spike sorting up to 5500 acquisition channels, 43x more than state-of-the-art alternatives, supporting 18KHz acquisition frequency. We present an experimental study on a commonly used reference dataset, using on-line refinement of the sorting clusters to improve accuracy up to 82%, with only 4% degradation with respect to off-line analysis. INDEX TERMS Field programmable gate arrays, Signal processing, Neural engineering, APSoC, HDMEA, Spike sorting.

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Section: Discussionmentioning

confidence: 99%

Section: Target Spike Sorting Pipelinementioning

confidence: 99%

Section: ) Spike Window Centering Explorationmentioning

confidence: 99%

Section: ) Spike Window Centering Explorationmentioning

confidence: 99%

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ZyON: Enabling Spike Sorting on APSoC-Based Signal Processors for High-Density Microelectrode Arrays

2020

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“…Thus, FPGAs may be better suited for use in these fields than ASICs. In the literature several FPGA-based solutions can be found, which were developed for spike sorting not suited to process data recorded with high-channel-count neural probes [12]- [18], while [19], [21]- [23] capable of sorting action potentials recorded with high spatial resolution probes [24], [25].…”

Section: Introductionmentioning

confidence: 99%

Spatial Information Based OSort for Real-Time Spike Sorting Using FPGA

Schäffer

Nagy

Kincses

et al. 2021

IEEE Trans. Biomed. Eng.

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Spiking activity of individual neurons can be separated from the acquired multi-unit activity with spike sorting methods. Processing the recorded high-dimensional neural data can take a large amount of time when performed on general-purpose computers. Methods: In this paper, an FPGAbased real-time spike sorting system is presented which takes into account the spatial correlation between the electrical signals recorded with closely-packed recording sites to cluster multichannel neural data. The system uses a spatial window-based version of the Online Sorting algorithm, which uses unsupervised template-matching for clustering. Results: The test results show that the proposed system can reach an average of 86% using simulated data (16-32 neurons, 4-10 dB Signal-to-Noise Ratio), while the single-channel clustering version achieves only 74% average accuracy in the same cases on a 128-channel electrode array. The developed system was also tested on in vivo cortical recordings obtained from an anesthetized rat. Conclusion: The proposed FPGA-based spike sorting system can process more than 11000 spikes/second, so it can be used during in vivo experiments providing real-time feedback on the location and electrophysiological properties of well-separable single units. Significance: The proposed spike sorting system could be used to reduce the positioning error of the closely-packed recording site during a neural measurement.

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