A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes

Kim, Sang-Min; Sobelman, Gerald E.; Lee, Hanho

doi:10.1109/tvlsi.2010.2043965

Cited by 44 publications

(30 citation statements)

References 10 publications

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“…Generally, an area scaling factor of (1.414 2 ) 2 ≈ 4 and a frequency scaling factor of 1.414 2 ≈ 2 is used to convert a 90-nm result to 180-nm result [6]. Thus, scaled area value for 96 × 96 network equals 0.1317 × 4 = 0.527 mm 2 , that translates to about 11% saving in terms of area compared to [5] and 27% compared to [3]. Scaled frequency value for 96 × 96 network equals 650 ÷ 2 = 325 MHz, which is about 38% and 70% higher than [5] and [3], respectively.…”

Section: Implementation and Comparison Resultsmentioning

confidence: 99%

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An efficient radix-4 Quasi-cyclic shift network for QC-LDPC decoders

Ajaz

Lee

2014

IEICE Electron. Express

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A Radix-4 Quasi-cyclic shift network (QSN) for reconfigurable QC-LDPC decoders is presented in this paper. A complexity reduction technique is described to reduce the total gate count at each stage in addition to the fact that Radix-4 logarithmic barrel shifter naturally offers less number of stages compared to Radix-2. The proposed Radix-4 QSN architecture supports various code rates and all sizes of sub matrices. Moreover, a novel Radix-4 signal generator is proposed which is particularly an essential element for reconfigurable LDPC decoders. The synthesis, placement and routing (P & R) of the proposed network is performed using TSMC 90-nm standard cell CMOS technology. The implementation results shows that the proposed network outperforms its predecessors by about 11% and 38% in terms of area and clock frequency respectively.

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Section: Implementation and Comparison Resultsmentioning

confidence: 99%

“…The switch network is one of the sources of complexity and critical path within LDPC decoders [1,2]. QC-LDPC codes simplify the switch network.…”

mentioning

confidence: 99%

An efficient radix-4 Quasi-cyclic shift network for QC-LDPC decoders

Ajaz

Lee

2014

IEICE Electron. Express

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“…In the case of a layered decoder, two types of messages require memory storage: the AP-LLR messages and the check node messages. A typical layered LDPC decoder [29][30][31][32][33], depicted in Figure 5, contains the following components:…”

Section: Layered Ldpc Decodersmentioning

confidence: 99%

“…Field -Programmable Gate Arraymessage to the AP-LLR update, a comparator for updating the check node message, and the addition unit for the AP-LLR update [29][30][31][32]. Specific FPGA optimization can be implemented within the combined processing unit, which includes the use of the 6-input LUT within the CLB for comparator implementation-the comparator is implemented as ROM memories [30]-as well as the usage of the dedicated shift register chains for the implementation of the FIFOs.…”

Section: Layered Ldpc Decodersmentioning

confidence: 99%

Design Trade‐Offs for FPGA Implementation of LDPC Decoders

Amăricăi¹,

Boncalo²

2017

Field - Programmable Gate Array

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Low density parity check (LDPC) decoders represent important throughput bottlenecks, as well as major cost and power-consuming components in today's digital circuits for wireless communication and storage. They present a wide range of architectural choices, with different throughput, cost, and error correction capability trade-offs. In this book chapter, we will present an overview of the main design options in the architecture and implementation of these circuits on field programmable gate array (FPGA) devices. We will present the mapping of the main units within the LDPC decoders on the specific embedded components of FPGA device. We will review architectural trade-offs for both flooded and layered scheduling strategies in their FPGA implementation.

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“…The MS algorithm brings up lower computational complexity for the CN update, using a minimum function [8] [9] described by eq.…”

Section: ) Min Sum Algorithmmentioning

confidence: 99%

Application specific hardware architecture for high-throughput short-length LDPC decoders

Belean

Nedevschi

Borda

2013

2013 IEEE 9th International Conference on Intelligent Computer Communication and Processing (ICCP)

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LDPC codes have been intensively used in various wireless communication applications, due to their increased BER performance. The present paper summarizes the state of the art applications of short length LDPC codes and proposes FPGA based application specific hardware architectures for shortlength LDPC decoders. The decoding algorithms considered for implementation are both belief propagation and min-sum algorithm. Due to the increased BER performances, the proposed architecture make use of parallel computation capabilities offered by FPGA technology in order to implement the belief propagation algorithm. In spite of the iterative nature and increased computational complexity of the LDPC decoding algorithm, the proposed architecture achieves high-throughput, mandatory in real-time application and data transmission. The architecture for the LDPC belief propagation based decoder is based on arctangent hyperbolic function approximation used for check nodes update.

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A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes

Cited by 44 publications

References 10 publications

An efficient radix-4 Quasi-cyclic shift network for QC-LDPC decoders

An efficient radix-4 Quasi-cyclic shift network for QC-LDPC decoders

Design Trade‐Offs for FPGA Implementation of LDPC Decoders

Application specific hardware architecture for high-throughput short-length LDPC decoders

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