A review: Hardware Implementation of AES using minimal resources on FPGA

Dhede, Onkar S.; Shah, Sanjeevani K.

doi:10.1109/pervasive.2015.7087187

Cited by 7 publications

(3 citation statements)

References 4 publications

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“…To tackle these issues, some IoT devices already provide hardware-based loosely coupled implementations of some security algorithms [27][28][29]. Nonetheless, the performance gains come at the cost of extra hardware added to the device.…”

Section: Aes Acceleratorsmentioning

confidence: 99%

FAC-V: An FPGA-Based AES Coprocessor for RISC-V

Gomes

Sousa

Silva

et al. 2022

JLPEA

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In the new Internet of Things (IoT) era, embedded Field-Programmable Gate Array (FPGA) technology is enabling the deployment of custom-tailored embedded IoT solutions for handling different application requirements and workloads. Combined with the open RISC-V Instruction Set Architecture (ISA), the FPGA technology provides endless opportunities to create reconfigurable IoT devices with different accelerators and coprocessors tightly and loosely coupled with the processor. When connecting IoT devices to the Internet, secure communications and data exchange are major concerns. However, adding security features requires extra capabilities from the already resource-constrained IoT devices. This article presents the FAC-V coprocessor, which is an FPGA-based solution for an RISC-V processor that can be deployed following two different coupling styles. FAC-V implements in hardware the Advanced Encryption Standard (AES), one of the most widely used cryptographic algorithms in IoT low-end devices, at the cost of few FPGA resources. The conducted experiments demonstrate that FAC-V can achieve performance improvements of several orders of magnitude when compared to the software-only AES implementation; e.g., encrypting a message of 16 bytes with AES-256 can reach a performance gain of around 8000× with an energy consumption of 0.1 μJ.

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Section: Aes Acceleratorsmentioning

confidence: 99%

FAC-V: An FPGA-Based AES Coprocessor for RISC-V

Gomes

Sousa

Silva

et al. 2022

JLPEA

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“…The circuit is described in a hardware description language, typically Verilog or VHDL [10], and it is synthesized and implemented on the target device through automated design tools. Typically, the FPGA fabric is composed from a large set of logic resources, such as lookup tables (LUT) [11], flip-flops (FF), input-output blocks (IOBs) and others, that are interconnected through configurable routing resources. The available hardware resources allow the implementation of highly parallel circuits for multiple controllers that can greatly accelerate computations on FPGAs compared to a microcontroller or DSP.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Scalable and Parametrizable Analog-to-Digital Converter on FPGA

2022

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The flexibility provided by FPGAs permits the implementation of several ADCs, each one configured with the required bit resolution and sampling frequency. The paper presents the design and implementation of scalable and parametrizable analog-to-digital converters (ADC), based on a successive approximation register (SAR), on FPGAs (field programmable gate arrays). Firstly, the work develops a systematic methodology for the implementation of a parametrizable SAR-based ADC from a set of building modules, such as the pulse-width modulator (PWM), external low-pass filter (LPF) and the analog comparator. The presented method allows choosing the LPF parameters for the required performance (resolution bits and sampling frequency) of a SAR-based ADC. Secondly, the paper also presents several optimizations on the PWM module to enhance the sampling frequency of implemented ADCs, and the method to choose the LPF parameters is adapted. The PWM and SAR logic are synthesizable and parametrizable, using a low number of resources, in order to be portable for low-cost FPGA families. The methodology and PWM optimizations are tested on a Zynq-7000 device from Xilinx; however, they can be adapted to any other FPGA.

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“…SCA is one of attack models that utilizes side informations to obtain the secret key. A cryptographic device is a device that implements cryptographic algorithms on a hardware [6][7][8]. Power analysis is a type of SCA attacks that can reveal confidential information [9].…”

Section: Introductionmentioning

confidence: 99%

Attacking AES-Masking Encryption Device with Correlation Power Analysis

Putra

Ahmad

Sutikno

et al. 2022

Int. j. commun. netw. inf. secur.

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Modern communication system use cryptography algorithm to ensure data still confidentiality, integrity, and authentic. There is a new vulnerability in a cryptographic algorithm when implemented on a hardware device. This vulnerability is considered capable of uncovering a secret key used in a cryptographic algorithm. This technique is known as a power analysis attack. Previous and other research introduces countermeasure to countering this new vulnerability. Some researchers suggest using logic level with encoding the AES. The countermeasure using logic is meager cost and efficient. The contribution of this paper is to analyze CPA on encryption device that has been given logic level countermeasure. Our finding of this paper is the use of encoding with one-hot masking technique does not provide the maximum countermeasure effect against CPA-based attacks. In this research, CPA attack can be successfully revealing the AES secret-key

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A review: Hardware Implementation of AES using minimal resources on FPGA

Cited by 7 publications

References 4 publications

FAC-V: An FPGA-Based AES Coprocessor for RISC-V

FAC-V: An FPGA-Based AES Coprocessor for RISC-V

Design and Implementation of Scalable and Parametrizable Analog-to-Digital Converter on FPGA

Attacking AES-Masking Encryption Device with Correlation Power Analysis

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