A Robust BBPLL-Based 0.18-$\mu$ m CMOS Resistive Sensor Interface With High Drift Resilience Over a −40 °C–175 °C Temperature Range

Marin, Jorge; Sacco, Elisa; Vergauwen, Johan; Gielen, Georges

doi:10.1109/jssc.2019.2911888

Cited by 16 publications

(14 citation statements)

References 24 publications

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“…This shows how power is traded off between the analog and digital portions of the ADC. An important design option to reduce the impact of flicker noise in a sensing application is to use chopping [39], as will be discussed in part 2 of this paper.…”

Section: A Noisementioning

confidence: 99%

Time-Encoding Analog-to-Digital Converters: Bridging the Analog Gap to Advanced Digital CMOS-Part 1: Basic Principles

Gielen

Hernández

Rombouts

2020

IEEE Solid-State Circuits Mag.

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I. MOTIVATION FOR TIME ENCODINGThe scaling of CMOS technology deep into the nanometer range has created challenges for the design of high-performance analog integrated circuits. The shrinking supply voltage and the presence of mismatch and noise restrain the dynamic range, causing analog circuits to be large in area and have a high power consumption in spite of the process scaling. Analog circuits based on time encoding [1], [2] and hybrid analog/digital signal processing [3] have been developed to overcome these issues. Realizing analog circuit functionality with highly digital circuits results in more scalable design solutions that can achieve excellent performance. This article reviews the basic principles of time encoding, in particular applied to analog-to-digital converters (ADCs) based on Voltage-Controlled Oscillators (VCOs), one of the most successful time-encoding techniques to date. Although VCO-based ADCs have been around for a long time [4], [5] they really received a significant boost in interest after Straayer and Perrotts highly cited 2008 paper [6]. Since then, many other advancements from different research groups worldwide have been published, in application domains such as sensor readout [7]-[10], telecom [11]-[13], wideband wireless [14]-[18], Internet of Things [19], automotive [20], [21], biomedical [22]-[24], to name a few. Note that the integrating properties of VCOs have also been used to implement continuous-time filters, time to digital converters and other analog signal processing blocks [25]-[27].This overview article is divided in two parts. This first part will introduce the basic principles of time encoding with emphasis on VCO-based ADCs, and will compare them to traditional analog circuits. The follow-up article (part 2) will describe and compare different time-encoding circuit architectures for analog-to-digital converters, and will discuss the corresponding design challenges of the building blocks. Together, they will demonstrate how time-encoding circuits can overcome many of the problems encountered when designing high-performance analog circuits that fully take advantage of advanced digital CMOS technologies, rather than suffering from it, hence bridging the analog gap to advanced CMOS. The main idea behind time encoding consists of representing an analog signal with a modulated square wave, where the signal information is encoded in the transitions instead of the instantaneous amplitude. Such a signal is easy to handle with digital circuits and is robust against noise and distortion. Representing the signal is then done through pulse modulations, known since long ago. Pulse Width Modulation (PWM) is one of the best examples, and used extensively in, for instance, power electronics. The typical block diagram of a time-encoding ADC is shown in Fig. 1. The analog input signal is applied to a pulse modulator that encodes the information in the pulse width, frequency or position of a signal (or set of signals) with two levels only. This two-level signal, which is still analog, ...

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Section: A Noisementioning

confidence: 99%

Time-Encoding Analog-to-Digital Converters: Bridging the Analog Gap to Advanced Digital CMOS-Part 1: Basic Principles

Gielen

Hernández

Rombouts

2020

IEEE Solid-State Circuits Mag.

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“…Fig. 3(b) illustrates this for the specific case of a differential resistive sensor configured in a Wheatstone bridge at the input, with the DAC feeding back to digitally controllable resistors in the bridge [13]. Compared to the basic structure of Fig.…”

Section: A Closed-loop Vco-based Architecturesmentioning

confidence: 99%

“…3(a) [12], or closing the loop around the Wheatstone bridge with resistive sensors in Fig. 3(b) [13].…”

Section: A Closed-loop Vco-based Architecturesmentioning

confidence: 99%

“…Two examples are shown in Fig. 8: in (a) both the VCOs and the phase detector are embedded inside the choppers [41], whereas in (b) only the VCOs are chopped [13]. The latter BBPLL-based design combines chopping with VCO tuning to largely remove the errors introduced by VCO mismatches and drift, resulting in ppm-level gain and offset drift due to power-supply and temperature variations across the entire -40 • C to +175 • C range.…”

Section: B Time-domain Choppingmentioning

confidence: 99%

“…The latter BBPLL-based design combines chopping with VCO tuning to largely remove the errors introduced by VCO mismatches and drift, resulting in ppm-level gain and offset drift due to power-supply and temperature variations across the entire -40 • C to +175 • C range. This high drift resilience can be established with only a single-temperature calibration scheme and without requiring external accurate references or components [13]. An alternative to chopping the actual VCOs is to perform the chopping in the VCO drivers in front of the actual VCO-based ADC [5], [42].…”

Section: B Time-domain Choppingmentioning

confidence: 99%

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