A scalable MPEG-4 video codec architecture for IMT-2000 multimedia applications

Takahashi, Masafumi; Nishikawa, Takafumi; Arakida, Hideho; Machida, Nobuya; Yamamoto, Hideki; Fujiyoshi, Toshihide; Matsumoto, Yoko; Yamagishi, O.; Samata, T.; Asano, A.; Terazawa, T.; Ohmori, Kenji; Shirakura, J.; Watanabe, Yoshinori; Nakamura, Hiroki; Minami, Shigenobu; Furuyama, T.

doi:10.1109/iscas.2000.856290

Cited by 10 publications

(8 citation statements)

References 3 publications

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“…Only in [14] it is possible to scale the architecture for better performance by adding modular processors to the system. All of the referred encoders utilize hardware accelerators to implement the entire encoder [13] or for the computation intensive operations [12,[14][15][16].…”

Section: Shared Memory Approachmentioning

confidence: 99%

“…For portable devices, programmability is often sacrificed for other design requirements. Most of those architectures rely on dedicated processing elements that give the highest processing efficiency with respect to the hardware usage and power consumption [12][13][14][15][16][17]. As a drawback, dedicated architectures are non-flexible as they are adapted to the processing of a specific algorithm.…”

Section: Introductionmentioning

confidence: 99%

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Scalable Architecture for SoC Video Encoders

Kangas

Hämäläinen

Kuusilinna

2006

J VLSI Sign Process Syst Sign Image Video Technol

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Evolving video coding standards demand functional flexibility for implementations, not only at design time but also after fabrication. This paper presents a System-on-Chip design approach with a feasible combination of performance, scalability, programmability, area efficiency, and design time effort for a video encoder. The encoder is based on a homogeneous master-slave processor architecture. Each slave encodes a part of the frame in the Single Program Multiple Data (SPMD) data parallel model. Both shared and distributed memory architectures are presented. Design effort is reduced by identical program codes, automated assembly of software and hardware modules independent of the number and type of processors, as well as our flexible on-chip communication network called Heterogeneous IP Block Interconnection (HIBI). A case study implementation with two to ten simple ARM7 processors, 32-bit HIBI bus and non-optimized processor-independent software gives the performance from 6 to 53 fps for QCIF. The whole encoder area ranges from 173 to 770 kgates excluding the memories. The relation scales reasonably well to systems with more powerful processors and optimized code. The optimization of the communication network shows that with more than six slaves even a serial HIBI connection with 100 MHz speed is feasible. HIBI and the parallelization approach allow exploration and optimization of the communication both at the application and architecture layers.

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Section: Shared Memory Approachmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Scalable Architecture for SoC Video Encoders

Kangas

Hämäläinen

Kuusilinna

2006

J VLSI Sign Process Syst Sign Image Video Technol

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show abstract

“…They consist of many dedicated hardware processing cores [1][2][3] such as a Discrete Cosine Transform (DCT), Inverse DCT (IDCT), Variable Length Coding (VLC), Quantizer (Q), inverse-Quantizer (IQ), Motion Compensator (MC) and Motion Estimator (ME) etc., which possess many different functions. Although large numbers of pins are required, the designer still has very limited access to each processing core inside the SoC.…”

Section: Introductionmentioning

confidence: 99%

An Infrastructural IP for Interactive MPEG-4 SoC Functional Verification

Adiono

Kerkhoff²,

Kunieda

2009

ijeei

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This paper introduces a specific architecture including an infrastructural IP for functional verification and diagnostics, which is suitable for functional core-based testing of an MPEG4 SoC. Our advanced MPEG4 SoC results in a high complexity SoC with limited physical access to many different functional cores. The proposed test method provides direct monitoring and control for each core, which enables core verification at actual speed. It significantly decreases the verification time due to the large number of required test vectors in typical MPEG4 verification. Furthermore, it also makes the system scalable for functional core expansion due to upgrading of standards. The proposed infrastructural IP is also linked to PCbased interactive tools to simplify the verification of individual and integrated cores. It also provides detailed diagnostic data that enables simple system debugging. The debugging tools also feature test-pattern generation and simulation of expected values. Actual system implementation has shown full functionality of our proposed method.

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“…Let us compare power consumption between a dedicateddesign approach and our programmable-DSP approach for MPEG-4. The dedicated MPEG-4 video codec LSI reported in [6] consumes 240 mW at 60-MHz clock frequency when it executes both SP@Ll video codec and speechcodec. The power consumption of 250-MHz SPXKS is dramatically lower than that of the dedicated MPEG-4 LSI, where a 250-MHz SPXK5 can handle both SP@L2 video codec and speech codec.…”

Section: Mpeg-4 Codecmentioning

confidence: 99%

“…The operations represented by Eqs. (5,6) are referred to as add-compareselect (ACS) operations. The speed of ACS operations is crucial to the successful implementation of a Viterbi decoder on a DSP.…”

Section: (5)mentioning

confidence: 99%

A low-power programmable DSP core architecture for 3G mobile terminals

Kumura

Ishii²,

Ikekawa³

et al.

2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221)

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We have developed a new-generation, general-purpose digital signal processor (DSP) core with low power dissipation for use in third-generation (3G) mobile terminals. The DSP core employs a 4-way VLIW (very long instruction word) approach, as well as a dual-multiply-accumulate (dual-MAC) architecture with good orthogonality. It is able to perform both video and speech codec for 3G wireless communications a t 384 k bidsec with a power consumption of approximately 50 mW. This paper presents an overview of both the DSP core architecture and a DSP instruction set, and it also gives some application benchmarks.

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A scalable MPEG-4 video codec architecture for IMT-2000 multimedia applications

Cited by 10 publications

References 3 publications

Scalable Architecture for SoC Video Encoders

Scalable Architecture for SoC Video Encoders

An Infrastructural IP for Interactive MPEG-4 SoC Functional Verification

A low-power programmable DSP core architecture for 3G mobile terminals

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