A self-consistent technique for the analysis of the temperature dependence of current–voltage and capacitance–voltage characteristics of a tunnel metal-insulator-semiconductor structure

Abstract

A new formalism is reported for the analysis of the current–voltage (I–V) characteristics of a tunnel metal-insulator-semiconductor (MIS) device, which considers a bias dependent distribution of interface states and barrier lowering due to the image force. Our theoretical expression for the I–V characteristics is general in the sense that it is applicable even under conditions when both the thermionic emission and the diffusion mechanisms of current transport compete with each other. The method is ideal for new epitaxial materials and devices where the carrier density is not known precisely beforehand. A self-consistent method of analysis is reported to determine the characteristic parameters of MIS diodes, using simultaneously the I–V and capacitance–voltage data as a function of temperature. This computational analysis has been used to examine the current transport mechanism in an Au/p-InP epitaxial MIS diode. The experimental verification of the theory and computational analysis is done by comparing the values of the interface state density distribution in thermal equilibrium with the semiconductor Nss, obtained from the forward I–V characteristics, with those directly measured by the multifrequency admittance method. Excellent agreement from these comparisons strongly supports the validity of the theory. Over the temperature range of 200–393 K, our results indicate that the interfacial layer-thermionic emission was clearly the dominant mechanism of the forward current transport in an MIS fabricated on a lightly doped InP:Zn epitaxial layer. The transmission coefficient through the insulator layer obtained from the reverse I–V characteristics was θp=1.43×10−3±7% from which we estimate an oxide thickness of 2.2 nm. The analysis of the barrier height φb0 versus temperature, obtained from 1 MHz C–V data provided a value φ0=1.06 V±10% for the zero bias and zero temperature barrier height.

All-printed diode operating at 1.6 GHz

“…This kind of MIS stack has been studied theoretically and experimentally with a precise control over the growth process and layer thicknesses in the past (36)(37)(38)(39)(40)(41)(42)(43). However, the numerical values calculated for different parameters in previous studies cannot be directly used for modeling and comparison here, because our device has a much different structure that includes particles with random shapes, oxide layers with inhomogeneous properties and the organic binder.…”

Examination by interfacial layer and inhomogeneous barrier height model of temperature-dependent I–V characteristics in Co/p-InP contacts

“…The˚a p and the ideality factor n for the device were obtained as 2.01 and 0.80 eV and 1.73 and 0.89 eV at 300 and 400 K, respectively. The high n values at high temperatures indicate the presence of a native oxide layer at the MS interface [4][5][6][7][8][9][10][11][32][33][34][35][36][37]. If semiconductor surfaces are prepared by the usual polishing and chemical etching, the semiconductor surface is inevitably covered with a thin native oxide layer of thickness about 10-20 Å.…”

“…If semiconductor surfaces are prepared by the usual polishing and chemical etching, the semiconductor surface is inevitably covered with a thin native oxide layer of thickness about 10-20 Å. Thus, the MS contacts formed under these conditions are not intimate contact because an interfacial layer of atomic dimensions inevitably separates them [4][5][6][7][8][9][10][11][32][33][34][35][36][37]. An ideality factor value of 2.01 usually leads to the film thicknesses of 15-20 Å [5-10,32-37].…”

“…It is well known that, unless specially fabricated, a SBD possesses a thin interfacial native oxide layer between the metal and the semiconductor. The existence of such an insulating layer converts the devices to metal-insulating-semiconductor (MIS) diode and may have a strong influence on the diode characteristics as well as a change of the interface state charge with bias which will give rise to an additional field in the interfacial layer [4][5][6][7][8][9][10][11][12]. Furthermore, inhomogeneities and/or residual processing-induced contamination in the interfacial region are commonly the reason for deviations from the ideal behavior in the electrical characteristics of Schottky contacts [11][12][13][14][15].…”

The analysis of the series resistance and interface states of MIS Schottky diodes at high temperatures using I–V characteristics

“…It has been well known that there have been currently a vast number of experimental and theoretical studies on the I-V characteristics of metal-semiconductor (MS), metal-insulatorsemiconductor (MIS) Schottky diodes and solar cells [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15]. The analysis of I-V characteristics of the Schottky diodes only at room temperature does not give detailed information about their current transport mechanisms or the nature of barrier formation at the MS interface.…”