A simple and efficient self-limiting erase scheme for high performance split-gate flash memory cells

Ahn, Byoung Jun; Sone, J.; Kim, J.W.; Choi, Insoo; Kim, D.M.

doi:10.1109/55.728905

Cited by 11 publications

(1 citation statement)

References 9 publications

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“…Such device structure is referred to as stack-gate flash memory. On the contrary, the split-gate planar channel flash memories with different L FG and L CG , L FG < L CG , have been reported (39,40). However, there have been no reported works regarding the fin-channel split-gate flash memories.…”

Section: Spilt-gate Flash Memory Structurementioning

confidence: 99%

(Invited) FinFET Flash Memory Technology

Liu¹,

Kamei

Matsukawa³

et al. 2012

ECS Trans.

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The crystal-Si and poly-Si fin-channel flash memories with a thin n+-poly-Si floating-gate (FG) layer have successfully been fabricated, and their electrical characteristics have systematically been investigated. It was experimentally found that the better short-channel effect (SCE) immunity, the smaller threshold voltage (Vt) variations and a higher program speed are obtained in the crystal-Si fin-channel tri-gate (TG)-type flash memories than in the double-gate (DG)-type ones. It was also confirmed that split-gate crystal-Si fin-channel flash memories show highly suppressed over-erase as compared to that in stack-gate memories. Moreover, it was found that Vt variation in the poly-Si fin-channel flash memories after a program/erase (P/E) cycle became comparable to that in the crystal-Si fin-channel memories. The measured source-drain breakdown voltage (BVDS) was higher than 3.2 V even the gate length (Lg) was down to 76 nm. The developed technology is very useful for the fabrication of scaled NOR-type flash memory.

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Section: Spilt-gate Flash Memory Structurementioning

confidence: 99%