A Single Analog-to-Digital Converter That Converts Two Separate Channels (I and Q) in a Broadband Radio Receiver

Garrity, Doug; Locascio, D. R.; Cavanagh, C.; Kabir, Mehdi; Guenther, C.

doi:10.1109/jssc.2008.922718

Cited by 12 publications

(3 citation statements)

References 17 publications

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“…Fig. 4 shows a schematic of the folded cascode opamp in the S/H circuit incorporating the proposed switching method with switched-capacitor common-mode feedback [10]. The drain node connections of the input transistors MI B and MI C are alternated between positive and negative output paths according to the switching configuration in Fig.…”

Section: B Proposed Dynamic Memory Effect Cancellationmentioning

confidence: 99%

A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique

Shin

Ahn

2011

IEEE Trans. Circuits Syst. II

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This brief presents a 10-bit 100-MS/s 1.2-V dualchannel pipelined CMOS analog-to-digital converter (ADC). The nine dual-channel pipelined stages share the operational amplifiers (op-amps) to optimize power and area. The proposed dynamic memory effect cancellation technique reduces the cross coupling caused by the residual charge in the op-amp sharing topology. The op-amp gain requirement of the dual-channel sample-and-hold circuit is also relaxed by the proposed memory effect cancellation technique. The prototype ADC achieves a peak signal-to-noise and distortion ratio of 56 dB for a 1-MHz input signal and a peak cross-coupling ratio of 67.4 dB at 100 MS/s while consuming 16.2 mW/channel from a 1.2-V supply. The prototype ADC occupies 1.96 mm 2 using a 0.13-μm CMOS technology. Index Terms-Dual channel, memory effect cancellation, op-amp sharing, pipelined analog-to-digital converter (ADC).

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Section: B Proposed Dynamic Memory Effect Cancellationmentioning

confidence: 99%

A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique

Shin

Ahn

2011

IEEE Trans. Circuits Syst. II

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“…Although the traditional pipeline ADC can achieve single perfect performance among accuracy, speed and power consumption, it is hard to meet these three requirements at the same time. For example, a couple of low-power pipeline ADC have been studied in [1] and [2], and it has been analyzed that a kind of pipeline ADC that has high sampling rate in [3], but the ADC related to these literature above can't have low power consumption and high sampling rate at the same time. In the wireless communication's occasion that requires high speed and low power driving voltage, such as ultrawideband wireless communication systems, those analog-digital converters are difficult to finish the assignment.…”

Section: Introductionmentioning

confidence: 99%

Design of High-Speed and Low-Power Two-Channel Pipeline ADC

Zhang

et al. 2011

AMR

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This paper describes a low-power 1.2 V 8-bit 1Gs/s two-channel pipeline ADC. The novelty of the designed ADC lies in: ameliorating the two-channel pipeline structure that consists of 1.5-bit multiplying DAC (MDAC). In order to reduce the power consumption and improve the sampling speed, the dual-channel pipeline Time Division Multiplexing operation amplifier and double or single channel flash ADC are used; in the front-end Sample-and-Hold circuits, switch-linearization control circuits(SLC) driven by a single clock signal is applied to solve the problem of time-skew and time mismatch between two channels. The pipeline ADC is designed with 90 nm CMOS process. From the simulation results of the designed ADC, we can draw that the SFDR is 42.3 dB; the SNR is 32.7 dB under the usual temperature. The ADC achieves 21 mW power-dissipation, 8 resolution and 1.01 GS/s sampling speed. So the design meets high speed, high precision and low power dissipation at the same time.

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“…Nowadays industry pays much attention to prevent failures that may interrupt production with severe consequences in cost, product quality, and safety. The work here presented the design and implementation of a low-cost SoC design that utilizes reconfigurable hardware and a customized embedded processor [4] for time-frequency analysis on industrial equipment through short-time Fourier transform and discrete wavelet transform [5]. Analog-to-Digital Converter (ADC) simultaneously converts two channels.…”

mentioning

confidence: 99%

FPGA SoC Based Multichannel Data Acquisition System with Network Control Module

Rajasekaran¹,

Jeyabharath²,

Veena³

2017

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Normally, Data acquisition (DAQ) is used to acquire the signals from different devices like sensors, transducers, actuators etc. The data acquisition is also used to analyze the signals, digitizing the signals and acquiring the signals from different inputs. The main drawbacks in data acquisition system are data storage, hardware size and remote monitoring. The System-on-Chip Field Programmable Gate Array (SoC-FPGA) is used in the proposed system in the aim to reduce the hardware and memory size. Further to provide remote monitoring with Ethernet/Wi-Fi, the Network Control Module (NCM) is integrated with Data acquisition and processing module for the communication between the systems. This developed system achieves high resolution with memory reduction, reduced hardware size, fast remote monitoring and control. It is used for real time processing in DAQ and signal processing. For fault tolerance and portability, the full system reconfigurability based FPGA acts as the best solution and the system can be reused with different configurations. The control of data acquisition and the subsequent management of data are coded in LabVIEW. LabVIEW tool is used to design and develop a fourchannel Data Acquisition and Processing (DAQP) unit. National Instruments Data Acquisition (NIDAQ) and National Instruments Field Programmable Gate Array (NIFPGA) are used to test and implement the design for real time processing. This is designed to provide high accuracy, storage and portability.

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A Single Analog-to-Digital Converter That Converts Two Separate Channels (I and Q) in a Broadband Radio Receiver

Cited by 12 publications

References 17 publications

A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique

A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique

Design of High-Speed and Low-Power Two-Channel Pipeline ADC

FPGA SoC Based Multichannel Data Acquisition System with Network Control Module

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