A single chip radix-2 FFT butterfly architecture using parallel data distributed arithmetic

Mactaggart, I.R.; Jack, Mervyn

doi:10.1109/jssc.1984.1052151

Cited by 16 publications

(3 citation statements)

References 3 publications

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“…Reduction was accomplished by the application of digit-serial arithmetic [3] and iterative multiplication architectures [4] wherever possible. An additional area savings was realized by the adaptation of a distributed arithmetic multiplier architecture presented in [5]. The multiplier architecture will be presented in more detail shortly.…”

Section: Pipelined Fft Architecturementioning

confidence: 99%

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A Pipelined, High-Precision FFT Architecture

Hopkinson¹,

Butler²

1992

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Publc reporting burden for this collection of inforiat~on is estimated to average 1 hour ner response. including the time for reviewing instructions, searching existing data sources, ga~thering and mantaining the data needed, and cOml:eting and revl~ing the collection of information. Approved for public release; distribution unlimited. ABSTRACT (Maximum 200 words)This paper presents a highly-integrated, high-precision FFT architecture. A 1.2 jm CMOS implementation of this architecture has yielded a 32-bit, 64K-point FFT that operates at a continuous 4-million-samples-per-second data rate. All FFT support functions, including coefficient generation and memory interfacing, are included on-chip.

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Section: Pipelined Fft Architecturementioning

confidence: 99%

“…Our multiplier is an adaptation of the distributed arithmetic architecture suggested by [5]. Rather than the naive complex multiplier configuration that requires four real multipliers and two real adders, the distributed arithmetic complex multiplier uses the equivalent of only two multipliers to compute a complex product.…”

Section: Multiplier Architecturementioning

confidence: 99%

A Pipelined, High-Precision FFT Architecture

Hopkinson¹,

Butler²

1992

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“…Very early results have shown that digital logic arrays integrated on SOS are 3-4 times faster than in bulk Si (Gehweiler and Schneider 1972). Various circuits have been fabricated: multipliers (Iwamura et a1 1983), static arithmetic units (Mactaggart and Jack 1984), programmable logic arrays (Horninger 1975), frequency synthesisers (Sunderland et a1 1984), etc. This rapid evolution allowed the emergence of SOS microprocessors.…”

Section: Performance Of Sos Devices and Comparison To Bulk Simentioning

confidence: 99%

Silicon films on sapphire

Cristoloveanu

1987

Rep. Prog. Phys.

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The physical properties of silicon on sapphire (SOS) thin films and their impact on the operation of integrated devices are systematically reviewed. The preparation of the SOS material is described from the fabrication of the sapphire substrate and the silicon film heteroepitaxy up to the .recently proposed regrowth techniques. The microscopic properties and the relevant methods used for inspection are discussed with emphasis on autodoping, stress, lattice defects and interface behaviour. Following the presentation of average transport and recombination parameters, deduced from measurements involving the contribution of the whole film, the non-homogeneity of the S O S film along the epitaxial direction will be outlined. The electrical properties of the silicon-sapphire interface and of the interfacial transition layer are compared to those of the front Si-SiO, interface. Attempts are made to correlate the data derived by various characterisation techniques in order to reveal a coherent image of the Si film volume sandwiched by two very dissimilar interfaces. Finally, the processing and the performance of SOS devices are discussed and favourably compared to the case of bulk Si technology.

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An expandable column fft architecture using circuit switching networks

Zhu

1993

J VLSI Sign Process Syst Sign Image Video Technol

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A single chip radix-2 FFT butterfly architecture using parallel data distributed arithmetic

Cited by 16 publications

References 3 publications

A Pipelined, High-Precision FFT Architecture

A Pipelined, High-Precision FFT Architecture

Silicon films on sapphire

An expandable column fft architecture using circuit switching networks

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