2001
DOI: 10.1109/16.930654
|View full text |Cite
|
Sign up to set email alerts
|

A small-signal RF model and its parameter extraction for substrate effects in RF MOSFETs

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1

Citation Types

0
4
0

Year Published

2003
2003
2016
2016

Publication Types

Select...
6
1
1

Relationship

0
8

Authors

Journals

citations
Cited by 41 publications
(4 citation statements)
references
References 7 publications
0
4
0
Order By: Relevance
“…After the VNA calibration, a set of deembedding devices (Open, Short and Thru) which exclude the SLG channel (but are otherwise identical to the GCPWs) are characterized using the same VNA parameter settings (such as power, intermediate frequency bandwidth, averaging factor, sweep time etc) as during SOLT measurements. The de-embedding devices enable removal of the effects of parasitic impedances from the apparent (or as-measured) response of the GCPWs [62][63][64]. The Open and Short de-embedding structures are used to extract C PS , R PO and C PO , as for figure 1(d).…”
Section: Resultsmentioning
confidence: 99%
“…After the VNA calibration, a set of deembedding devices (Open, Short and Thru) which exclude the SLG channel (but are otherwise identical to the GCPWs) are characterized using the same VNA parameter settings (such as power, intermediate frequency bandwidth, averaging factor, sweep time etc) as during SOLT measurements. The de-embedding devices enable removal of the effects of parasitic impedances from the apparent (or as-measured) response of the GCPWs [62][63][64]. The Open and Short de-embedding structures are used to extract C PS , R PO and C PO , as for figure 1(d).…”
Section: Resultsmentioning
confidence: 99%
“…So there may be some error occurred. At low frequencies the MOS structure is in thermal equilibrium under small signal ac excitation provided that minority carriers can respond to variations in the AC field to prevent energy loss [32][33][34][35]. The increase in capacitance in inversion only occurs if the generation/recombination of electrons can keep up with the applied ac signal.…”
Section: Resultsmentioning
confidence: 99%
“…To fabricate metal-oxide-semiconductor, the silicon wafers were cleaned by following the standard cleaning procedure to remove insoluble organics and metallic contaminants. After that, a layer of oxide, approximately 650 Å thick, was grown on the silicon wafers using a dry oxidation process at 950˚C for 2 hour, with a pre-ramp and post-ramp of 800˚C with N 2 (12) and O 2 (32). For top layer we will use Aluminum due to its ease of processing, ability to reduce native SiO 2 , which is always present in silicon wafers, exposed to atmosphere and its low resistivity.…”
Section: Process For Measurements Of Device Parametersmentioning
confidence: 99%
“…For the given design of DP4T DG RF CMOS switch capacitance model under the operating condition is shown in Figure 5. Here we consider the ON status, because the insertion loss is conquered by its ON-resistance and substrate resistance [16,17]. Isolation of the switch is finite due to signal coupling through the parasitic and junction capacitances.…”
Section: Capacitive Model Of Dp4t Dg Rf Cmos Switchmentioning
confidence: 99%