A stacked split word-line (SSW) cell for low-voltage operation, large capacity, high speed SRAMs

Ikeda, Shuji; Asayama, K.; Hashimoto, N.; Fujita, E.; Yoshida, Yoshinori; Koike, A.; Yamanaka, Toshiaki; Ishibashi, K.; Meguro, S.

doi:10.1109/iedm.1993.347276

Cited by 8 publications

(1 citation statement)

References 7 publications

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“…To meet access time and standby current requirements, MOSFET design must emphasize high performance and low leakage. The severe trade-off between onand off-currents is met with separate optimization of memory and logic NMOS FETs [2]. Low voltage bitcell operation was studied using circuit simulation and was improved by avoiding the P/N poly diode between the PMOS TFT and NMOS latch transistor with a tungsten interpoly plug and by using an LDD resistor [3] to improve bitcell stability.…”

Section: Introductionmentioning

confidence: 99%

High performance 0.25 μm SRAM technology with tungsten interpoly plug

McNelly

Hayden²,

Perera³

et al.

Proceedings of International Electron Devices Meeting

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A high performance 0.25pm CMOS process has been developed for fast static RAMS, featuring retrograde wells, shallow trench isolation with 0.55pm active pitch, a 55A nitrided gate oxide, 0.25pm polycide gate surface channel NMOS and PMOS transistors with drive currents of 630 and 300 pNpm respectively at an off-leakage of 10 pNpm, overgated TFTs with an odoff ratio greater than 6.1 05, stacked capacitors for improved SER, five levels of polysilicon planarized by chemicalmechanical polishing (CMP), with two self-aligned interpoly contacts and a tungsten interpoly plug (WIP) that connects 3 poly layers without parasitic diodes, 0.35 pm contacts and a 0.625pm metal pitch. A split word-line bitcell was scaled to an area of 3.74pm2 using 0.25pm design rules.

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Section: Introductionmentioning

confidence: 99%