A Stepped Oxide Hetero-Material Gate Trench Power MOSFET for Improved Performance

Abstract

In this brief, we propose a new stepped oxide heteromaterial trench power MOSFET with three sections in the trench gate (an N + poly gate sandwiched between two P + poly gates) and having different gate oxide thicknesses (increasing from source side to drain side). The different gate oxide thickness serves the purpose of simultaneously achieving the following: 1) a good gate control on the channel charge and 2) a lesser gate-to-drain capacitance. As a result, we obtain higher transconductance as well as reduced switching delays, making the proposed device suitable for both RF amplification and high-speed switching applications. In addition, the sandwiched gate with different work-function gate materials modifies the electric field profile in the channel, resulting in an improved breakdown voltage. By using 2-D simulations, we have shown that the proposed device structure exhibits about 32% enhancement in breakdown voltage, 25% reduction in switching delays, 20% enhancement in peak transconductance, and 10% reduction in figure of merit (product of ON-resistance and gate charge) as compared to the conventional trench-gate MOSFET.

Double trenches LDMOS with trapezoidal gate

“…We can obtain the gate charge curves and the Q GD of different devices by the simulated test circuit (shown in the inset figure of Fig. 7) with Medici software [16]. The Q GD of TGDT LDMOS and TG LDMOS is least.…”

A Novel Trench-Gated Power MOSFET With Reduced Gate Charge

“…Gate charge of the device affects the switching loss and the switching speed. To minimize the switching loss and increase the switching speed, it is required to reduce the gate charge [10], [12]. Fig.…”

“…Another method is the use of a split-gate in trench [8], [9], which makes the gate-drain coupling change into gate-source coupling. The new trench structure with different gate oxide thickness and different gate electrode materials [10] is proved to be an effective way for reducing gate-drain charge.…”

Investigation of laterally single-diffused metal oxide semiconductor (LSMOS) field effect transistor

“…Investigation of Laterally Single-diffused Metal Oxide Semiconductor (LSMOS) Field Effect Transistor 7 LDMOS to have a better gate control and that of C GD should be less as it acts as a miller capacitance [32][33][34]. The calculated value of C GS and C GD for the LSMOS are 12.7 nF/mm 2 and 2206.1 nF/mm 2 and for the LDMOS are 12.9 nF/mm 2 and 1260.4 nF/mm 2 , respectively.…”