A Study on Non-volatile 3D Stacked Memory for Big Data Applications

Qian, Cheng; Huang, Libo; Xie, Peng; Xiao, Nong; Wang, Zhiying

doi:10.1007/978-3-319-27119-4_8

Cited by 4 publications

(4 citation statements)

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“…Recently, the growing importance of reconfigurable electronic systems , and a wide range of bioinspired electronic applications promoted intense research in developing electronic devices with dynamically reconfigurable properties. − Unlike conventional electronic devices that operate with fixed characteristics, these emerging applications often demand devices with tunable characteristics and reconfigurable functionalities. ,,− Most of the research activities in this field so far have been focused on developing logic switches with reconfigurable behaviors, ,− while it is also highly desired to develop memory devices with dynamic tunability in their key performance parameters such as the channel carrier polarity and the programmed/erased state current ratios. Nonvolatile (NV) charge-trap memory is a popular type of solid-state memory technology − due to its excellent data storage performance and device scalability.…”

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confidence: 99%

“…R ecently, the growing importance of reconfigurable electronic systems 1,2 and a wide range of bioinspired electronic applications promoted intense research in developing electronic devices with dynamically reconfigurable properties. 3−7 Unlike conventional electronic devices that operate with fixed characteristics, these emerging applications often demand devices with tunable characteristics and reconfigurable functionalities.…”

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A Dynamically Reconfigurable Ambipolar Black Phosphorus Memory Device

et al. 2016

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Nonvolatile charge-trap memory plays an important role in many modern electronics technologies, from portable electronic systems to large-scale data centers. Conventional charge-trap memory devices typically work with fixed channel carrier polarity and device characteristics. However, many emerging applications in reconfigurable electronics and neuromorphic computing require dynamically tunable properties in their electronic device components that can lead to enhanced circuit versatility and system functionalities. Here, we demonstrate an ambipolar black phosphorus (BP) charge-trap memory device with dynamically reconfigurable and polarity-reversible memory behavior. This BP memory device shows versatile memory properties subject to electrostatic bias. Not only the programmed/erased state current ratio can be continuously tuned by the back-gate bias, but also the polarity of the carriers in the BP channel can be reversibly switched between electron- and hole-dominated conductions, resulting in the erased and programmed states exhibiting interchangeable high and low current levels. The BP memory also shows four different memory states and, hence, 2-bit per cell data storage for both n-type and p-type channel conductions, demonstrating the multilevel cell storage capability in a layered material based memory device. The BP memory device with a high mobility and tunable programmed/erased state current ratio and highly reconfigurable device characteristics can offer adaptable memory device properties for many emerging applications in electronics technology, such as neuromorphic computing, data-adaptive energy efficient memory, and dynamically reconfigurable digital circuits.

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A Dynamically Reconfigurable Ambipolar Black Phosphorus Memory Device

et al. 2016

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“…Huang et al [108] evaluated a 3D heterogeneous storage structure that tightly integrates CPU, DRAM, and a flashbased NVM to meet the memory needs of big data applications, i.e., larger capacity, smaller delay, and wider bandwidth. Processing near heterogeneous memories is a new research topic with high potential (could provide the best of both worlds), and in the future, we expect much interest in this direction.…”

Section: Open Issues and Future Directionsmentioning

confidence: 99%

Near-memory computing: Past, present, and future

Singh

Chelini

Corda

et al. 2019

Microprocessors and Microsystems

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The conventional approach of moving data to the CPU for computation has become a significant performance bottleneck for emerging scale-out data-intensive applications due to their limited data reuse. At the same time, the advancement in 3D integration technologies has made the decade-old concept of coupling compute units close to the memory -called nearmemory computing (NMC) -more viable. Processing right at the "home" of data can significantly diminish the data movement problem of data-intensive applications.In this paper, we survey the prior art on NMC across various dimensions (architecture, applications, tools, etc.) and identify the key challenges and open issues with future research directions. We also provide a glimpse of our approach to near-memory computing that includes i) NMC specific microarchitecture independent application characterization ii) a compiler framework to offload the NMC kernels on our target NMC platform and iii) an analytical model to evaluate the potential of NMC.

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“…Huang et al [139] propose a 3D hybrid storage structure that tightly integrates CPU, DRAM, and Flash-based NVRAM to meet the memory needs of big data applications with larger capacity, smaller delay and wider bandwidth. Similar to scale-out processors' pod [116], DRAM and NVM layers are divided into multiple zones, corresponding to their core sets.…”

Section: Processing In Hybrid 3d-stacked Dram and Nvrammentioning

confidence: 99%

Performance characterization and optimization of in-memory data analytics on a scale-up server

Awan¹

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The sheer increase in volume of data over the last decade has triggered research in cluster computing frameworks that enable web enterprises to extract big insights from big data. While Apache Spark defines the state of the art in big data analytics platforms for (i) exploiting data-flow and in-memory computing and (ii) for exhibiting superior scale-out performance on the commodity machines, little effort has been devoted at understanding the performance of in-memory data analytics with Spark on modern scale-up servers. This thesis characterizes the performance of in-memory data analytics with Spark on scale-up servers. Through empirical evaluation of representative benchmark workloads on a dual socket server, we have found that in-memory data analytics with Spark exhibit poor multi-core scalability beyond 12 cores due to thread level load imbalance and work-time inflation. We have also found that workloads are bound by the latency of frequent data accesses to DRAM. By enlarging input data size, application performance degrades significantly due to substantial increase in wait time during I/O operations and garbage collection, despite 10% better instruction retirement rate (due to lower L1 cache misses and higher core utilization). For data accesses we have found that simultaneous multi-threading is effective in hiding the data latencies. We have also observed that (i) data locality on NUMA nodes can improve the performance by 10% on average, (ii) disabling next-line L1-D prefetchers can reduce the execution time by up-to 14%. For GC impact, we match memory behaviour with the garbage collector to improve performance of applications between 1.6x to 3x. and recommend to use multiple small executors that can provide up-to 36% speedup over single large executor. Based on the characteristics of workloads, it envisions nearmemory and near storage hardware acceleration to improve the single-node performance of scale-out frameworks like Apache Spark. Using modelling approaches, it estimates the speed-up of 5x for Apache Spark using near data hardware acceleration. El gran aumento del volumen de datos en la última década (conocido como Big Data) ha desencadenado un gran esfuerzo de investigación en el marco de la computación en clúster, permitiendo a las empresas de Internet extraer conocimiento de dicho Big Data. Actualmente Apache Spark representa el estado del arte en cuanto a plataformas de análisis de Big Data (i) por su capacidad de explotar la computación data-flow con datos in-memory, y (ii) por un rendimiento y escalado con el numero de procesadores adecuado en las arquitecturas comerciales actuales. Sin embargo, poco esfuerzo se ha dedicado a entender dicho rendimiento y justificar los principales factores que estarían limitándolo en los servidores escalables de hoy en día. Esta tesis caracteriza el rendimiento de estos entornos de análisis de datos en memoria basados en Spark. A través de una evaluación empírica, utilizando cargas de trabajo de referencia y representativas, en un servidor de doble socket, se ha concluido una falta de escalabilidad más allá de los 12 núcleos, básicamente debida a desequilibrios de la carga de trabajo a nivel de threads (flujos de ejecución), al aumento del tiempo de ejecución de cada core respecto a la ejecución secuencial, y la latencia de los accesos de los datos que residen en la memoria DRAM. Al aumentar el tamaño de los datos de entrada, el rendimiento de la aplicación se reduce significativamente debido al aumento en el tiempo de espera durante las operaciones de E/S y el garbage collector (GC), a pesar que la finalización de las instrucciones mejora en un 10% (debido a una menor tasa de fallo de la memoria caché L1 y mayor utilización de los núcleos del procesador).Para tolerar la latencia en los accesos a los datos, se ha concluido que el multi-threading simultáneo resulta eficaz y que (i) la mejora de la localidad a nivel de nodos NUMA puede mejorar el rendimiento en un 10% en promedio y (ii) deshabilitar la pre-búsqueda de datos a nivel de L1-D puede reducir el tiempo de ejecución del orden del 14%. En cuanto al impacto del GC, se observa que es posible mejorar el rendimiento de las aplicaciones en un factor entre 1.6x y 3x a base de utilizar múltiples pequeños ejecutores en vez de un único gran ejecutor. En base a los resultados y análisis realizados en las cargas de trabajo utilizadas, la tesis doctoral analiza las posibilidades de utilizar unidades de cálculo cercanas a la memoria (near-memory) y a los dispositivos de almacenamiento (near-storage), mejorando así el rendimiento de los nodos que se utilicen para la ejecución de Apache Spark. Se presenta un modelo que estima una mejora de 5x en el rendimiento de Apache Spark usando aceleradores hardware cercanos a los datos.

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A Study on Non-volatile 3D Stacked Memory for Big Data Applications

Cited by 4 publications

References 25 publications

A Dynamically Reconfigurable Ambipolar Black Phosphorus Memory Device

A Dynamically Reconfigurable Ambipolar Black Phosphorus Memory Device

Near-memory computing: Past, present, and future

Performance characterization and optimization of in-memory data analytics on a scale-up server

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