A Study on self-timed asynchronous subthreshold logic

Lotze, Niklas; Ortmanns, Maurits; Manoli, Yiannos

doi:10.1109/iccd.2007.4601949

Cited by 12 publications

(11 citation statements)

References 15 publications

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“…In practice, implementing digital circuits with digital completion detection properties bring circuit overhead due to the inherent redundancy for generating the completion detection signal. Recently in [7] Lotze et al examined self-timed asynchronous circuits operating in the sub-threshold regime. They implemented and simulated dual-rail multipliers with different bit-widths.…”

Section: B Asynchronous Operationmentioning

confidence: 99%

“…Based on the findings in [7], we updated the circuit model parameters from the energy model in [6] to reflect dual-rail operation. The results of our numerical simulations showing the energy profile of ISCAS85 benchmark circuits for synchronous, singlerail and dual-rail implementations are shown in Figure 1.…”

Section: B Asynchronous Operationmentioning

confidence: 99%

“…However, asynchronous circuit families with inherent digital completion detection incur both area and energy dissipation overhead. Especially in the sub-threshold regime energy increase due to higher leakage is more pronounced [7]. In this work we focus on the implementation and de-synchronization flow development of single-rail circuits that operate with current sensing completion detection.…”

Section: Introductionmentioning

confidence: 99%

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Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study

Akgun

Rodrigues

Sparsø

2010

2010 IEEE Symposium on Asynchronous Circuits and Systems

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Abstract-This paper addresses the design of self-timed energy-minimum circuits, operating in the sub-VT domain. The paper presents a generic implementation template using bundled-data circuitry and current sensing completion detection. To support this, a fully-decoupled latch controller has been developed, which integrates the current sensing circuitry. The paper outlines a corresponding design flow, which is based on contemporary synchronous EDA tools, and which transforms a synchronous design, into a corresponding self-timed circuit. The design flow and the current-sensing technique is validated by the implementation of an asynchronous version of a wavelet based event detector for cardiac pacemaker applications in a standard 65 nm CMOS process. The chip has been fabricated and the area overhead due to power domain separation and completion detection circuitry is 13.6 %. The improvement in throughput due to asynchronous operation is 52.58 %. By trading the throughput improvement, energy dissipation is reduced by 16.8 % at the energy-minimum supply voltage.

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Section: B Asynchronous Operationmentioning

confidence: 99%

Section: B Asynchronous Operationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study

Akgun

Rodrigues

Sparsø

2010

2010 IEEE Symposium on Asynchronous Circuits and Systems

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“…Kritisch sind in diesem Zusammenhang zum einen die Ausgangspegel der verwendeten Logikgatter, wodurch besondere Anforderungen an die Transistordimensionierung entstehen (Wang and Chandrakasan, 2004) (Lotze et al, 2007). Abbildung 2 zeigt eine grafische Darstellung des notwendigen Overheads.…”

Section: Introductionunclassified

“…Es wurde deshalb eine Simulationsmethode entwickelt, die die Variabilitäten einzelner Gatter in VHDL abbildet und auf diesem Wege erlaubt, den Aufwand der Monte-Carlo-Simulation auf die Logikebene zu verschieben. Eine genauere Beschreibung dieser Vorgehensweise findet sich in Lotze et al (2007).…”

Section: Introductionunclassified

Untersuchung von asynchronen Timing-Strategien für digitale Subthreshold-Schaltungen

Lotze¹,

Ortmanns²,

Manoli³

2008

Adv. Radio Sci.

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Abstract. Eine der großen Herausforderungen beim Betrieb von Schaltungen bei extrem niedrigen Versorgungsspannungen ist die starke Zunahme des Einflusses zufälliger Prozessvariationen auf die Verzögerungszeiten der Gatter. Dies erfordert sehr hohe Sicherheitsmargen im Timing der Schaltungen, was zu einer deutlichen Verringerung der Geschwindigkeit und einem Anstieg der Energie pro Operation führt. Asynchrone Schaltungstechniken, die durch ihre Kodierung das Ende einer Operation detektieren können, sind daher bei dieser Anwendung eine interessante Alternative. In dieser Veröffentlichung werden die notwendigen Sicherheitsmargen in Delay-Line basierten Subthreshold-Schaltungen diskutiert und mögliche asynchrone Dual-Rail Entwurfsmethoden vorgestellt. Transistor-Level Simulationsergebnisse für einen einfachen, in den diskutierten Techniken realisierten Zähler werden vorgestellt, um die Funktionsfähigkeit dieser Techniken im Subthreshold-Bereich zu demonstrieren. Multiplizier mit unterschiedlicher Wortbreite dienen als Beispiel für eine komplexere Schaltung, welche bezüglich Geschwindigkeit, Energiebedarf und Flächenaufwand mit einer entsprechenden Standard-Realisierung verglichen wird, was abschließend eine Aussage darüber zulässt, wann die untersuchten Techniken gewinnbringend eingesetzt werden können.

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Ultra‐low power pass‐transistor‐logic‐based delay line design for sub‐threshold applications

2016

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Designs that operate at sub-threshold voltages are a promising response to the ultra-low power demands of many modern applications with relaxed performance requirements. Towards this approach, a pass-transistor-logic-based programmable delay line (DL) circuit is presented that is designed specifically for sub-threshold operation. Compared with the commonly used design, the DL consumes 79.2% less dynamic energy, 83.5% less leakage power, 47.2% better linearity across codewords, 58.6% smaller active area, and with similar resiliency to variations across Monte Carlo simulations.

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A Study on self-timed asynchronous subthreshold logic

Cited by 12 publications

References 15 publications

Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study

Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study

Untersuchung von asynchronen Timing-Strategien für digitale Subthreshold-Schaltungen

Ultra‐low power pass‐transistor‐logic‐based delay line design for sub‐threshold applications

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