A new trend in complex SoC design is chiplet-based IP reuse using 2.5D integration. In this paper we present a highly-integrated design flow that encompasses architecture, circuit, and package to build and simulate heterogeneous 2.5D designs. We chipletize each IP by adding logical protocol translators and physical interface modules. These chiplets are placed/routed on a silicon interposer next. Our package models are then used to calculate PPA and signal/power integrity of the overall system. Our design space exploration study using our tool flow shows that 2.5D integration incurs 2.1x PPA overhead compared with 2D SoC counterpart.

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Designs that operate at sub-threshold voltages are a promising response to the ultra-low power demands of many modern applications with relaxed performance requirements. Towards this approach, a pass-transistor-logic-based programmable delay line (DL) circuit is presented that is designed specifically for sub-threshold operation. Compared with the commonly used design, the DL consumes 79.2% less dynamic energy, 83.5% less leakage power, 47.2% better linearity across codewords, 58.6% smaller active area, and with similar resiliency to variations across Monte Carlo simulations.