A Sub-GHz Multi-ISM-Band ZigBee Receiver Using Function-Reuse and Gain-Boosted N-Path Techniques for IoT Applications

Lin, Zhicheng; Mak, Pui-In; Martins, Rui P.

doi:10.1007/978-3-319-21524-2_5

Cited by 35 publications

(8 citation statements)

References 19 publications

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“…In this receiver implementation, the LO phase noise is traded for low power consumption. On the other hand, the achieved noise figure of 9 dB for a −20-dBm blocker located 40-MHz offset is competitive with the reported performance of other state-of-the-art low-power RXs-a 13.7-dB NF for a −20-dBm blocker at a 50-MHz offset [33] and an 18-dB NF for a −10-dBm blocker at a 400-MHz offset [17]. In addition, the targeted IoT standards, such as Bluetooth and NB-IoT, expect their receivers to tolerate −27-dBm/−30-dBm blocker at 80-/60-MHz offset.…”

Section: Blocker Noise Figurementioning

confidence: 62%

Low-Power High-Linearity Mixer-First Receiver Using Implicit Capacitive Stacking With 3× Voltage Gain

Purushothaman

Klumperink

Plompen

et al. 2022

IEEE J. Solid-State Circuits

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In this article, we present a passive mixer-first receiver front end providing a low-power integrated solution for high interference robustness in radios targeting Internetof-Things (IoT) applications. The receiver front end employs a novel N-path filter/mixer, a linear baseband amplifier, and a step-up transformer to realize sub-6-dB NF and >20-dBm OB-IIP3 concurrently. The proposed N-path filter/mixer exploits an implicit capacitive stacking principle to achieve passive voltage gain of 3 during down-conversion and high out-ofband linearity simultaneously while using at least 2× less total capacitance for the same RF bandwidth compared to a conventional switch-capacitor N-path filter. Fabricated in 22-nm complementary metal-oxide-semiconductor (CMOS) fully depleted silicon on insulator (FDSOI), the receiver prototype-including a 2:6 transformer-occupies only 0.2 mm 2 of active area. Operating in the frequency range of 1.8-2.8 GHz, the front end provides a 45-47-dB conversion gain and a baseband bandwidth of 2 MHz. Due to passive voltage gain in the filter/mixer and transformer, the implemented front end consumes only 1.7-2.5 mW of power to achieve <6-dB NF, ∼24/60/1 dBm out-of-band IIP3/IIP2/B1dB, respectively.

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Section: Blocker Noise Figurementioning

confidence: 62%

Low-Power High-Linearity Mixer-First Receiver Using Implicit Capacitive Stacking With 3× Voltage Gain

Purushothaman

Klumperink

Plompen

et al. 2022

IEEE J. Solid-State Circuits

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“…On the other hand, the achieved blocker NF of 10 dB for a −15 dBm blocker is competitive with other sub-mW RF front-ends. For example, the 1.15 mW RX, reported in [24], achieves a blocker NF of 13.7 dB for a −20 dBm blocker located at 50 MHz offset.…”

Section: Blocker Tolerancementioning

confidence: 99%

“…Low power CMOS receivers typically employ high-Q external filters (e.g., SAW, FBAR) or off-chip and on-chip LC resonant tanks to attenuate the blockers and improve their OOB selectivity [17]- [23]. Recently N-path filters and feedback cancellations [24], [25] are adopted to improve the RF filtering and enhance the linearity performance of the RX. With power consumption ≤ 5 mW, these RXs exhibit OOB IIP3 between -20 and 0 dBm.…”

Section: Introductionmentioning

confidence: 99%

A Fully Passive RF Front End With 13-dB Gain Exploiting Implicit Capacitive Stacking in a Bottom-Plate N-Path Filter/Mixer

Purushothaman

Klumperink

Clavera

et al. 2020

IEEE J. Solid-State Circuits

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A low-power interferer-robust mixer-first receiver front-end that uses a novel capacitive stacking technique in a bottom-plate N-path filter/mixer is proposed. Capacitive stacking is achieved by reading out the voltage from the bottom-plate of N-path capacitors instead of their top-plate, which provides a 2x voltage gain after down-conversion. A step-up transformer is used to improve the out-of-band (OOB) linearity performance of small switches in the N-path mixer, thereby reducing the power consumption of switch drivers. This paper explains the concept of implicit capacitive stacking and analyzes its transfer characteristics. A prototype chip, fabricated in 22 nm FDSOI technology, achieves a voltage gain of 13 dB and OOB IIP3/IIP2 of +25/+66 dBm with 5 dB Noise figure while consuming only 600 µW of power at fLO=1 GHz. Thanks to the transformer, the prototype can operate in the input frequency range of 0.6-1.2 GHz with more than 10 dB voltage gain and 5-9 dB Noise figure. Thus it opens up the possibility of low-power software defined radios.

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“…However, such cells also exhibit a high NF and insufficient linearity owing to the limited linearity of the active mixer and lack of RF filtering. A receiver architecture employing a function-reuse RF front-end and a CR VCO-filter cell has been proposed [7]; however, the NF of this architecture is also relatively high, and the in-band input 1-dB compression point is -50 dBm because of the low supply voltage of 0.5 V. Low-power receiver architectures in which the dc bias current of an RF LNTA and baseband (BB) stage is shared were also developed [8]- [11]. An RF-to-BB-CR receiver incorporating an RF bandpass filter with an eight-path passive mixer was proposed [8] to improve the linearity of the architecture.…”

Section: Introductionmentioning

confidence: 99%

2.4 GHz BLE Receiver With Power-Efficient Quadrature RF-to-Baseband-Current-Reuse Architecture for Low-Power IoT Applications

Park

Kwon

2021

IEEE Access

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In this paper, a 2.4 GHz Bluetooth low energy receiver employing a power-efficient quadrature RF-to-baseband-current-reuse architecture is presented for low-power low-voltage internet of things applications. The proposed quadrature RF-to-baseband-current-reuse RF front-end consists of a lownoise transconductance amplifier, an active-type polyphase filter-based quadrature generator, transimpedance amplifiers, and double-balanced current-mode passive mixers on a single dc current path. An input matching network is used to perform power-constrained simultaneous noise and input power matching and 1/f noise reduction in the RF and baseband domains, respectively. The quadrature RF signals are provided to the single-quadrature mixers through an embedded active-type polyphase filter-based quadrature generator. The implemented Bluetooth low energy receiver is composed of the RF-to-basebandcurrent-reuse RF front-end, IF amplifiers, two-stage passive-RC polyphase filter, and fifth-order Chebyshev-II G m -C filters. The proposed design was fabricated using a 65-nm CMOS process and characterized primarily in the Bluetooth low energy operating frequency bands. The active die area of the implemented receiver was 0.85 mm 2 , and the receiver drew a bias current of 1.41 mA from a nominal supply voltage of 0.8 V. The Bluetooth low energy receiver achieved a noise figure of 13.2 dB, conversion gain of 42 dB, image rejection ratio of more than 30 dB, and input-referred third-order intercept point of −25 dBm.INDEX TERMS Active-type polyphase filter, bias-current sharing, Bluetooth low energy, current-reuse, image rejection ratio, IoT, I/Q mismatch, low-IF receiver, low-voltage, non-invasive filter, quadrature generator, quadrature transconductor, RF-to-BB-current-reuse

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A Sub-GHz Multi-ISM-Band ZigBee Receiver Using Function-Reuse and Gain-Boosted N-Path Techniques for IoT Applications

Cited by 35 publications

References 19 publications

Low-Power High-Linearity Mixer-First Receiver Using Implicit Capacitive Stacking With 3× Voltage Gain

Low-Power High-Linearity Mixer-First Receiver Using Implicit Capacitive Stacking With 3× Voltage Gain

A Fully Passive RF Front End With 13-dB Gain Exploiting Implicit Capacitive Stacking in a Bottom-Plate N-Path Filter/Mixer

2.4 GHz BLE Receiver With Power-Efficient Quadrature RF-to-Baseband-Current-Reuse Architecture for Low-Power IoT Applications

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