A superscalar RISC processor with pseudo vector processing feature

Abstract

A novel architectural extension, in which floatingpoint dara are t r&med directly from main memory to floating-point registers, has been successfully implemented in a superscalar RISC processor. This extension allows main memory access throughput of I .2 Gbytels, and efective perjonnance reaches 267 MFLOPS (89% of the peakpei$omce) for typical floating-point applications. The processor utilizes 0.3-micron 4-level metal CMOS technology with 2.5 V power supply and contains 3.9 million transistors in 15.7 mm x 15.7 mm die size. Only 4.5% of the die area is used for the extension. Pipeline stage optimization and swreboardbased dependency check method allow the extension to be realized without affecting the operating frequency.

Instruction fetch and dispatch scheme with flag-in-cache/in-IBR

“…There are 32-bit integer registers in two integer ALUs and 32 registers with 4 read and 3 write functions. Moreover, 64-bit floating registers are 128 with 4 read and 4 write along with adder/subtractor, multiplier/divider [12,13]. Cache memory has two stages.…”