A Survey of Hybrid Techniques for Functional Verification

Bhadra, Jayanta; Abadir, Magdy S.; Wang, Li-C.; Ray, Sandip

doi:10.1109/mdt.2007.30

Cited by 40 publications

(20 citation statements)

References 36 publications

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“…There is some academic and industrial research on semiformal verification, which consists of a standard language specifying correctness criteria and design and vector generation based on constraints [6]. The constraints are derived according to the given language and design.…”

Section: Related Workmentioning

confidence: 99%

Simulation-Based Hardware Verification with a Graph-Based Specification

Chen

Wang

2018

Mathematical Problems in Engineering

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Simulation-based verification continues to be the primary technique for hardware verification due to its scalability and ease of use; however, it lacks exhaustiveness. Although formal verification techniques can exhaustively prove functional correctness, they are limited in terms of the scale of their design due to the state-explosion problem. Alternatively, semiformal approaches can involve a compromise between scalability, exhaustiveness, and resource costs. Therefore, we propose an event-driven flow graph-based specification, which can describe the cycle-accurate functional behaviors without the exploration of whole state space. To efficiently generate input sequences according to the proposed specification, we introduce a functional automatic test pattern generation (ATPG) approach, which involves the proposed intelligent redundancy-reduction strategy to solve problems of random test vectors. We also proposed functional coverage criterion based on the formal specification to support a more reliable measure of verification. We implement a verification platform based on the proposed semiformal approach and compare the proposed semiformal approach with the constrained randomized test (CRT) approach. The experiment results show that the proposed semiformal verification method ensures a more exhaustive and effective exploration of the functional correctness of designs under verification (DUVs).

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Section: Related Workmentioning

confidence: 99%

Simulation-Based Hardware Verification with a Graph-Based Specification

Chen

Wang

2018

Mathematical Problems in Engineering

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“…We believe that Bluespec SystemVerilog presents an interesting focus for further research in formal hardware verification; BSV programs are naturally amenable to expression in formal logic, which raises the possibility of relatively painless experimentation with a broad range of automated formal and semi-formal methods [6]. Possibilities for further work include:…”

Section: Further Workmentioning

confidence: 99%

A monadic approach to automated reasoning for Bluespec SystemVerilog

Richards

Lester

2011

Innovations Syst Softw Eng

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We embed a non-trivial subset of Bluespec SystemVerilog (BSV) in the higher order logic of the PVS theorem prover. Owing to the clean semantics of BSV, application of monadic techniques leads to a surprisingly elegant embedding, in which hardware designs are translated into logic almost verbatim, preserving types and language constructs. The resulting specifications are compatible with the builtin model checker of PVS, which can automatically prove an important class of temporal logic theorems, and can also be used in conjunction with the powerful proof strategies of PVS, including automatic predicate abstraction, to verify a broader class of properties than can be achieved with model checking alone. Bluespec SystemVerilog is a hardware description language based on the guarded action model of concurrency. It has an elegant semantics, which has previously been shown to support design verification by hand proof: to date, however, little work has been conducted on the application of automated reasoning to BSV designs.

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“…Traditional verification techniques based on direct testbenches (where the test traffic is typically hand-written in HDL as a sequence of input vectors; output vectors are calculated a priori and then matched with the ones monitored from the DUT) or on formal demonstrations are inefficient when dealing with complex designs made up of multiple heterogeneous IP cores [1][2][3][4][5]. Direct testbenches are applied to the DUT by means of simulation; they have a poor level of automation since most testing traffic scenarios are usually hand-written; even using more highlevel programming languages (such as C++ or SystemC) to abstract the set of possible significant stimuli, the problem of checking (i.e.…”

Section: Introductionmentioning

confidence: 99%

“…Then, under the assumption of some hypotheses (typically represented by some set of stimuli) and with the help of an analysis tool, the formal verification approach tries to prove one or more theorems (on those stimuli, the DUT always behaves in the desired manner). This approach does not need simulations (though recently also symbolic simulations have been introduced combining formal techniques with standard simulation [1]) and is general enough to treat also corner cases. However, formal verification proved to be too complex for medium or large sized designs because the set of properties that the verification engineer needs to formally demonstrate is huge; the well known state explosion problem limits model checking, and the cost of theorem proving is prohibitive because of the amount of skilled manual guidance it requires.…”

Section: Introductionmentioning

confidence: 99%

“…the foreseen utilization scenarios. While code coverage is about ensuring that all part of the RTL netlist (statements, expressions, branches, finite machine states, block instantiations) have been stimulated by the test vectors (automatic measure of achieved code coverage is already supported in recent EDA tools for HDL IP simulations), functional verification requires a major verification engineering effort [1][2][3][4][5]. Indeed, functional verification is about (i) catching functional behaviour of the DUT from the specifications document and (ii) validating that DUT behaviour for all possible working scenarios (input traffic and internal IP state) is consistent with its specification.…”

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confidence: 99%

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Coverage-Driven Verification of HDL IP Cores

Saponara

Vitullo

Petri

et al. 2011

Lecture Notes in Electrical Engineering

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The progress of nanometric CMOS technologies and design methodologies has fostered the development of complex digital designs, thanks to the capability of integrating an increasing number of IP cores within a single chip. This trend made one typical issue of the embedded and digital systems design flow to become more and more critical: the exhaustive functional verification of complex systems. In fact, as system complexity grows, the same is for verification tasks which have two main crucial points: (i) generating proper testing scenarios that stress key features of the DUT (Design Under Test) and (ii) determining the amount of different tests needed to reach enough coverage (code and functional) to assert that the DUT is bug free w.r.t. the foreseen utilization scenarios. While code coverage is about ensuring that all part of the RTL netlist (statements, expressions, branches, finite machine states, block instantiations) have been stimulated by the test vectors (automatic measure of achieved code coverage is already supported in recent EDA tools for HDL IP simulations), functional verification requires a major verification engineering effort [1][2][3][4][5]. Indeed, functional verification is about (i) catching functional behaviour of the DUT from the specifications document and (ii) validating that DUT behaviour for all possible working scenarios (input traffic and internal IP state) is consistent with its specification. To be noted that code and

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A Survey of Hybrid Techniques for Functional Verification

Cited by 40 publications

References 36 publications

Simulation-Based Hardware Verification with a Graph-Based Specification

Simulation-Based Hardware Verification with a Graph-Based Specification

A monadic approach to automated reasoning for Bluespec SystemVerilog

Coverage-Driven Verification of HDL IP Cores

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