A Test Methodology for Neural Computing Unit

Cheong, Minho; Lee, Ingeol; Kang, Sungho

doi:10.1109/isocc.2018.8649896

Cited by 3 publications

(3 citation statements)

References 3 publications

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“…Note that, after post-manufacturing testing [14,15], the host control circuit can establish information about faulty PEs. Then, throughout the circuit's lifespan, the number of faulty PEs may increase as the circuit ages.…”

Section: Fault-tolerance Mechanism and Corresponding Pe Architecturementioning

confidence: 99%

“…Note that these hardware failures are caused by latent manufacturing defects [10,11] or circuit aging effects [12,13], potentially resulting in functional errors. We can employ post-manufacturing testing mechanisms [14,15] to identify latent manufacturing defects. Additionally, run-time detection mechanisms [16,17] can be used to identify the effects of circuit aging.…”

Section: Introductionmentioning

confidence: 99%

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Highly Fault-Tolerant Systolic-Array-Based Matrix Multiplication

Lu,

Su,

Huang

2024

Electronics

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Matrix multiplication plays a crucial role in various engineering and scientific applications. Cannon’s algorithm, executed within two-dimensional systolic arrays, significantly enhances computational efficiency through parallel processing. However, as the matrix size increases, reliability issues become more prominent. Although the previous work has proposed a fault-tolerant mechanism, it is only suitable for scenarios with a limited number of faulty processing elements (PEs). This paper introduces a pair-matching mechanism, assigning a fault-free PE as a proxy for each faulty PE to execute its tasks. Our fault-tolerant mechanism comprises two stages: in the first stage, each fault-free PE completes its designated computations; in the second stage, computations intended for each faulty PE are executed by its assigned fault-free PE proxy. The experimental results demonstrate that compared to the previous work, our approach not only significantly improves the fault tolerance of systolic arrays (applicable to scenarios with a higher number of faulty PEs) but also reduces circuit areas. Therefore, the proposed approach proves effective in practical applications.

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Section: Fault-tolerance Mechanism and Corresponding Pe Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Highly Fault-Tolerant Systolic-Array-Based Matrix Multiplication

Lu,

Su,

Huang

2024

Electronics

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show abstract

“…The key takeaway is that majority of the cores will be matched to the expected response and can distinguish the minority cores with faulty response through majority analyzer. A method for concurrent error checking between neighboring elements in a systolic array is presented in [26]. This requires additional XOR logic for output comparisons between neighboring elements and may result in an increased test area overhead.…”

Section: Related Workmentioning

confidence: 99%

Test Architecture for Systolic Array of Edge-Based AI Accelerator

et al. 2021

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The application diversity and evolution of AI accelerator architectures require innovative DFT solutions to address issues such as test time, test power, performance and area overhead. Full scan DFT, because of its enhanced controllability and observability, is an industrial de facto test strategy. However, it may not yield an optimal test solution with stringent design constraints of edge-based AI accelerators. In this paper, a novel test architecture based on selective-partial scan is proposed for performance, power and area (PPA) overhead constrained edge-based systolic AI accelerator. In this architecture, the structural test patterns are applied partly in functional manner, which reduces the testability problem of an array to that of a single processing element (PE); thus, resulting in reduced test time and test data volume. Moreover, a delay fault testing method based on Launch-on-Capture is presented for the partial scan based proposed architecture. Experimental results show that proposed architecture is efficient in terms of test power and test time when compared to full scan DFT.

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