A Three-Mask-Processed Coplanar a-IGZO TFT With Source and Drain Offsets

13.3L: Late‐News Paper: Roll‐to‐Roll Processed and Top‐Gate‐Structured Amorphous InGaZnO TFTs with Large Source/Drain Offsets

“…In contrast to the prior report in case of a short length of the S/D offset under 5 m, the large amount of the current drop should be happened in our work. [10,11] Besides, we cannot do another surface treatment at the offset region, because the region is not revealed during three-mask photolithography process. Therefore, three-mask processed TFTs via R2R processing only describe a limited performance, because of the large value of S/D offset length.…”

“…Therefore, it can be applied not only a switching/driving TFT in the pixel, but also high speed circuit in the panel. [9][10][11] Lee et al reported that a top gate and coplanar structure can be simply fabricated by three masks process, but the longer length of the S/D offset length, the lower the device performance has been showed. However, they only investigated the effect of the length of S/D offset under 5 m. As we mentioned before, typically, the L2L margin determining S/D offset length is at least 5 m in the R2R alignment, which corresponding to the S/D offset length more than 10 m. [1,4] The large value of the S/D offset length restricts current flow due to the large series resistance of the active layer, resulting in low device performance.…”

A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

“…The main approach to lower the leakage current and suppress the kink effect is to reduce the device drain side electric field. Several designs have been proposed and studied to reduce the drain electric field and improve device performance, including offset gate [6,7], lightly-doped drain (LDD) [8,9], and field-induced drain (FID) [10,11] TFTs. However, offset gate TFT sacrifices the On-state current, due to an increased parasitic resistance, and FID design often needs an extra mask and one more field bias, which complicates the device biasing scheme.…”

“…However, offset gate TFT sacrifices the On-state current, due to an increased parasitic resistance, and FID design often needs an extra mask and one more field bias, which complicates the device biasing scheme. In the same vein, the LDD structure has higher On-state current than the offset one and the LDD design often needs additional implantation process and suffers ion implantation damage and difficulty in controlling the doping in grain boundary [7,8,12]. A raised source/drain (RSD) structure is an alternative approach to lower device leakage current and drain side electric field effectively, without degrading On-state current seriously [4,12].…”

P.22: Improving Switching Characteristics of Amorphous‐InGaZnO4 Thin‐Film Transistors by Dual‐Gate Driving

“…Amorphousindium-gallium-zinc-oxide (a-IGZO) is the most-favored AOS because of its many advantages, which include low deposition temperature, high electron mobility, high on/off switching characteristics, and large optical band gap. Many groups have explored various device structures in order to fully optimize the advantages of the a-IGZO material [1]- [6]. Device stability has also been the focus of many researchers [7], and as a result, most of them are now starting to understand the negative bias under illumination stress (NBIS) instability, which has been the major drawback [8]- [10].…”