A Time-Interleaved Track &amp;#x00026; hold in 0.13 &amp;#x003BC;m CMOS sub-sampling a 4 GHz signal with 43 dB SNDR

Louwsma, S.M.; Tuijl, E.J.M. van; Vertregt, M.; Nauta, Bram

doi:10.1109/cicc.2007.4405745

Cited by 11 publications

(10 citation statements)

References 6 publications

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“…Integration of both techniques also can be used with other objectives. Louwsma et al [48] propose a time-interleaved multichannel track and hold for a subsampling-based SDR receiver, with 48 dB of SNDR at 1.35 GS/s. This technique can be used to increase the total sampling rate as well.…”

Section: Cognitive Radiomentioning

confidence: 99%

“…This technique can be used to increase the total sampling rate as well. In this case, Louwsma et al [48] propose to apply subsampling directly at the first track and hold. Furthermore, digital calibration techniques are usually employed only for band-limited signals in the first Nyquist band, so that they cannot be directly applied for band-pass-sampling schemes.…”

Section: Cognitive Radiomentioning

confidence: 99%

See 1 more Smart Citation

Analog‐to‐Digital Conversion for Cognitive Radio: Subsampling, Interleaving, and Compressive Sensing

Oya¹,

Chavero²,

Martı́n-Clemente³

2017

Cognitive Radio

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This chapter explores different analog-to-digital conversion techniques that are suitable to be implemented in cognitive radio receivers. This chapter details the fundamentals, advantages, and drawbacks of three promising techniques: subsampling, interleaving, and compressive sensing. Due to their major maturity, subsampling-and interleavingbased systems are described in further detail, whereas compressive sensing-based systems are described as a complement of the previous techniques for underutilized spectrum applications. The feasibility of these techniques as part of software-defined radio, multistandard, and spectrum sensing receivers is demonstrated by proposing different architectures with reduced complexity at circuit level, depending on the application requirements. Additionally, the chapter proposes different solutions to integrate the advantages of these techniques in a unique analog-to-digital conversion process.

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Section: Cognitive Radiomentioning

confidence: 99%

Section: Cognitive Radiomentioning

confidence: 99%

Analog‐to‐Digital Conversion for Cognitive Radio: Subsampling, Interleaving, and Compressive Sensing

Oya¹,

Chavero²,

Martı́n-Clemente³

2017

Cognitive Radio

View full text Add to dashboard Cite

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“…In this paper, we propose a new calibration scheme for timing mismatch in undersampling (or sub-sampling) TIADCs, which can be applicable for sub-sampling receivers, software defined radios, and broadband satellite receivers [11]. The alldigital correction and estimation algorithms are implemented using a polyphase architecture.…”

Section: Introductionmentioning

confidence: 99%

All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition

Duc

Nguyen

Jabbour

et al. 2016

IEEE Trans. Circuits Syst. II

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This paper proposes a new all-digital calibration technique suppressing the timing mismatch effect in Time-Interleaved Analog-to-digital Converters (TIADCs) for input at any Nyquist Band (NBs) using the equivalent polyphase structure of the TIADC. The correction technique is simple and does not require the adaptive digital synthesis filters. The timing mismatch is estimated based on an adaptive stochastic gradient descent technique, which is a promising solution for TIADCs operating at very fast sampling rate. The digital circuit of the proposed calibration algorithm is designed and synthesized using 28nm FD-SOI CMOS technology for the 11-bit, 60dB SNR TIADC clocked at 2.7GHz with the input in the first four NBs. The designed circuit occupies the area of 0.05mm 2 and dissipates the total power of 41mW.

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“…To dissolve these problems, several reports [1] present the correlator based architecture adopting the delay generator such as DLL (Delay Locked Loop) circuit. As an alternative solution, the sub-sampling architecture or equivalent time sampling is considerable and the timing clock can be generated from the DLL [2]. In later case, DLL makes the clocks spaced at equal and fine time offset (several tens ps).…”

Section: Introductionmentioning

confidence: 99%

“…However, the repeated process requires too much time and the high resolution monitoring may be impractical. Hence, 4-channel time interleaved samplers, which is already adopted in the reference [2], is also used in this work. Using the time interleaved sampler the monitoring time becomes 4 times shorter than the single channel architecture.…”

Section: Introductionmentioning

confidence: 99%

A 3 ~ 5 GHz CMOS UWB Radar Chip for Surveillance and Biometric Applications

Lee¹,

Ha²,

Yoo³

et al. 2011

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A 3-5 GHz UWB radar chip in 0.13 m CMOS process is presented in this paper. The UWB radar transceiver for surveillance and biometric applications adopts the equivalent time sampling architecture and 4-channel time interleaved samplers to relax the impractical sampling frequency and enhance the overall scanning time. The RF front end (RFFE) includes the wideband LNA and 4-way RF power splitter, and the analog signal processing part consists of the high speed track & hold (T&H) / sample & hold (S&H) and integrator. The interleaved timing clocks are generated using a delay locked loop. The UWB transmitter employs the digitally synthesized topology. The measured NF of RFFE is 9.5 dB in 3-5 GHz. And DLL timing resolution is 50 ps. The measured spectrum of UWB transmitter shows the center frequency within 3-5 GHz satisfying the FCC spectrum mask. The power consumption of receiver and transmitter are 106.5 mW and 57 mW at 1.5 V supply, respectively.

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A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR

Cited by 11 publications

References 6 publications

Analog‐to‐Digital Conversion for Cognitive Radio: Subsampling, Interleaving, and Compressive Sensing

Analog‐to‐Digital Conversion for Cognitive Radio: Subsampling, Interleaving, and Compressive Sensing

All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition

A 3 ~ 5 GHz CMOS UWB Radar Chip for Surveillance and Biometric Applications

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