A Unified Framework for Instruction Scheduling and Mapping for Function Units with Structural Hazards

Performance evaluation for a compressed-VLIW processor

“…However, despite the merits, the SVLIW processor has a performance limit the same as the-VLIW processor because the SVLIW processor can't execute the next long inslruetiun until all inst3"uctinns within the scheduled long inslruction are executed. To solve the performance limit problem, a processor arc, hiteclta'e thai satisfies the following criteria is required: (1) load balance between compile-time and nm-lLme pmallelization, (2) individual inslruedon scheduling, and 0) reducing the size of object code [2]. This paper presents a new ILP prtw, essor architecture called a Compressed VLIW (CVLIW) processor architecUa'e that achieves these goals.…”

“…-58113-445-2/02/03...$5.00 the other hand, the VLIW processor ¢onmucts a pmallelized long instruction sequence at compile-time [1,8]. Tberefor~ the VLIW processor can be implemented using simple hardware units, but object code is more complex since it conlains groups of long instructions each of which is composed of a number of insmu~on~ The VLIW processor has performance bottlenecks due to the unoplimized Imge object code and compulso D, instruction scheduling [2,6,7]. To balance a load between compile-time and run-time on the above processors, 3uperscalar VLIW (SVLIW) processor architecture has been studied.…”