1988
DOI: 10.1109/4.5947
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A variable delay line PLL for CPU-coprocessor synchronization

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Cited by 218 publications
(63 citation statements)
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“…As a consequence, the NOR gate delay can be controlled. An interested reader is referred to [2] for further details. Fig.…”
Section: Variable Delay Elements: Design Techniquesmentioning
confidence: 99%
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“…As a consequence, the NOR gate delay can be controlled. An interested reader is referred to [2] for further details. Fig.…”
Section: Variable Delay Elements: Design Techniquesmentioning
confidence: 99%
“…In some applications, we need a delay which can be controlled digitally [2], [4], [9]. The current starved circuit can be modified for this purpose.…”
Section: Variable Delay Elements: Design Techniquesmentioning
confidence: 99%
See 1 more Smart Citation
“…The differential inverter is a PMOS-input source-coupled differential amplifier with variable resistance loads as pulldown devices. The two-sided differential gain, A DM , is given by (1) where g m is the PMOS transconductance and R L is the resistance of the pull-down device. The differential gain determines the switching time and, as a result, the minimum…”
Section: Schematicsmentioning
confidence: 99%
“…These changes highlight the fact that increases in communication speed lead to ever smaller domains across which one must synchronize clocks. The problem of synchronizing clocks between a microprocessor and its peripherals led to the development of the first delay locked loop (DLL) for the MIPS R3000 chip set in 1988 [1]. The use of the phase locked loop (PLL), common for decades in FM demodulators, became ubiquitous for synchronizing clocks across a single large integrated circuit by the late 1990's.…”
Section: Introductionmentioning
confidence: 99%