Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time

Voyiatzis, Ioannis; Gizopoulos, Dimitris; Paschalis, A.

doi:10.1109/tvlsi.2005.857159

Cited by 25 publications

(23 citation statements)

References 30 publications

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“…To overcome these problems, FBIST methods have been proposed which exploit specific functional units like adders, multipliers, Arithmetic Logic Units (ALU) or processor cores for on-chip pseudorandom test generation and test response evaluation [21][22][23][24]. These units are available in data-path architectures used in traditional general purpose processors and in digital signal processing units.…”

Section: State-of-the-art Of Self-test Techniquesmentioning

confidence: 99%

Environment for the analysis of functional self-test quality in digital systems

Ubar¹,

Kostin²,

Kruus³

et al. 2014

Proc. Estonian Acad. Sci.

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Dependability of computer architectures has become one of the most important engineering concerns. One of the possibilities to increase the dependability is to develop architectures with dedicated self-test capabilities which allow achieving high quality of testing in terms of fault coverage. We propose a new methodology for Built-in Self-Test (BIST), which combines the inherent functionality of the architecture with a small amount of pre-generated test data stored in the memory, and uses for monitoring of the test process a restricted number of test points, configured as a set of signature analysers. Contrary to the traditional scan-path based logic BIST, the proposed solution does not need additional hardware for test pattern generation, and will not have any impact on the working performance of the system. On the other hand, testing at normal working conditions allows exercising the system on-line and at-speed, facilitating the detection of dynamic faults like delays and crosstalks to achieve high test quality. The new self-test method is free from the negative aspect of over-testing, compared to the traditional logic BIST approaches. A method is presented to generate optimized test data for selected test routines, and to choose minimum set of testpoints for response analysis. A tool framework is proposed to emulate self-testing architectures, and to carry out fault simulation for evaluating the test quality in terms of fault coverage.

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Section: State-of-the-art Of Self-test Techniquesmentioning

confidence: 99%

Environment for the analysis of functional self-test quality in digital systems

Ubar¹,

Kostin²,

Kruus³

et al. 2014

Proc. Estonian Acad. Sci.

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“…On the other hand, barrel shifter is the in-built component of many computing systems as it can shift multiple bits in a single cycle and hence it attains much importance in designing the processors [5], low-density parity-check decoders [6], optical networks [18] and test generation [19]. Among the various barrel shifters, logarithmic shifter has the simplest structure which is also more area efficient as it doesn't require any underneath decoder circuitry [20].…”

Section: Introductionmentioning

confidence: 99%

Optimized fault tolerant designs of the reversible barrel shifters using low power MOS transistors

et al. 2015

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This paper demonstrates the reversible logic synthesis for the unidirectional, bidirectional and universal barrel shifters. The proposed shifters are constructed using only Fredkin and Feynman double gates. Initially, these two gates are designed and schematized using standard low power p-MOS 901 and n-MOS 902 models with average channel length 45 nm, delay 0.030 ns and density 1200 kgates/mm 2 . These schemas can detect faulty signal in its primary outputs. Thus, all the proposed shifters inherently tolerate single level fault. Moreover, the presented generalized algorithm for the proposed unidirectional barrel shifter has further been used to build base structures of the proposed bidirectional and universal shifters. In addition, lower bounds on the numbers of constant inputs and garbage outputs of the reversible barrel shifter have been proposed. It has been evidenced that the proposed circuits are constructed with these optimum constant inputs and garbage outputs. The simulation results prove the functional correctness of the proposed circuits. The comparative results show that the proposed designs perform much better and have significantly better scalability than the existing approaches. B Md. Shamsujjoha

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“…As a result zero power dissipation would be achieved if a logic circuit consists of reversible gates. Reversible logic can easily be manipulated for Fault Testing [5], Embedded Devices [7], Digital Signal Processing [8], Quantum Dot Cellular Automata [9][10], etc.…”

Section: Introductionmentioning

confidence: 99%