Adaptation of stepped frequency continuous waveform to range-Doppler algorithm for SAR signal processing

Işıker, Hakan; Özdemir, Caner

doi:10.1016/j.dsp.2020.102826

Cited by 11 publications

(3 citation statements)

References 20 publications

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“…Also, a lowcomplexity solution is introduced to implement the heavy stage of Stolt interpolation. The advantage of developing RMA in this work is that it provides better performance than the chirp [26][27][28]. Especially under near-field (NF) conditions, the CSA and the RDA create a defocused image; because they can only partially correct the range curvature.…”

Section: Introductionmentioning

confidence: 99%

Development of Fast Fourier-Compatible Image Reconstruction for 3D Near-Field Bistatic Microwave Imaging With Dynamic Metasurface Antennas

Molaei

Fromentèze

Skouroliakou

et al. 2022

IEEE Trans. Veh. Technol.

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Emerging dynamic metasurface antennas (DMAs) technology promises to achieve future wireless communications by reducing hardware costs, physical size and power consumption. Especially in the field of radar imaging, they can be used as an effective alternative platform for modern computational imaging; because they can simplify the physical hardware and increase the data acquisition rate. Fourier transform (FT)-based scene image reconstruction techniques are known as cost-effective computing solutions for the imaging system processing unit. However, due to the physical layer compression in DMAs and the fact that they do not produce uniform radiation patterns, the information provided by them is not compatible with Fourier-based techniques and cannot be applied directly. In this paper, we first introduce a 3D near-field bistatic imaging approach using two one-dimensional (1D) DMAs as a panel-to-panel model in a Mills Cross structure. Then, based on the introduced mathematical model, we derive a Fourier-based algorithm for the image reconstruction problem. The proposed algorithm consists of five main steps: pre-processing (to transfer data provided by the transmitter and receiver DMAs to a set of equivalent spatial measurements), applying FTs to the transferred signal, filtering in the Fourier domain, a simplified interpolation, and applying a 3D inverse FT to retrieve scene information. The results of numerical simulations confirm the satisfactory performance of the proposed approach.

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Section: Introductionmentioning

confidence: 99%

Development of Fast Fourier-Compatible Image Reconstruction for 3D Near-Field Bistatic Microwave Imaging With Dynamic Metasurface Antennas

Molaei

Fromentèze

Skouroliakou

et al. 2022

IEEE Trans. Veh. Technol.

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show abstract

“…The matrix transpose transforms a given matrix by interchanging its rows and columns so that the rows become columns and the columns become rows. Matrix transpose is regularly used in SAR imaging to compute the 2D FFT [19][20][21][22][23]. First, the 1D FFT is performed along each row of a matrix; then, the matrix is transposed; afterwards, the 1D FFT is applied along each row; finally, the matrix is transposed one more time to put the resultant array in the correct order.…”

Section: Hls Ip For Matrix Transposementioning

confidence: 99%

“…As proof of concept, we present a FPGA accelerator in charge of the reordering stage of VEC-FFT [18], a software-optimized version of the FFT. Among the most frequently employed SAR focusing techniques, we can find the range-doppler algorithm [19,20], CS [8,9], and Omega-K (ω-k) [21][22][23], along with their extended versions. Common to all these methods is the use of the FFT, which has a high computational cost as it involves many additions, subtractions, and multiplications.…”

Section: Introductionmentioning

confidence: 99%

Towards On-Board SAR Processing with FPGA Accelerators and a PCIe Interface

Baungarten-Leon

Martín-del-Campo-Becerra

Ortega-Cisneros

et al. 2023

Electronics

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This article addresses a novel methodology for the utilization of Field Programmable Gate Array (FPGA) accelerators in on-board Synthetic Aperture Radar (SAR) processing routines. The methodology consists of using High-Level Synthesis (HLS) to create Intellectual property (IP) blocks and using the Reusable Integration Framework for FPGA Accelerators (RIFFA) to develop a Peripheral Component Interconnect express (PCIe) interface between the Central Processing Unit (CPU) and the FPGA, attaining transfer rates up to 15.7 GB/s. HLS and RIFFA reduce development time (between fivefold and tenfold) by using high-level programming languages (e.g., C/C++); moreover, HLS provides optimizations like pipeline, cyclic partition, and unroll. The proposed schematic also has the advantage of being highly flexible and scalable since the IPs can be exchanged to perform different processing routines, and since RIFFA allows employing up to five FPGAs, multiple IPs can be implemented in each FPGA. Since Fast Fourier Transform (FFT) is one of the main functions in SAR processing, we present a FPGA accelerator in charge of the reordering stage of VEC-FFT (an optimized version of FFT) as a proof of concept. Results are retrieved in reversed bit order, and the conventional reordering function may consume more than half of the total clock cycles. Next, to demonstrate flexibility, an IP for matrix transposition is implemented, another computationally expensive process in SAR due to memory access.

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An integrated FIR adaptive filter design by hybridizing canonical signed digit (CSD) and approximate booth recode (ABR) algorithm in DA architecture for the reduction of noise in the sensor nodes

Arumugam¹,

Paramasivan²

2021

Multidim Syst Sign Process

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Adaptation of stepped frequency continuous waveform to range-Doppler algorithm for SAR signal processing

Cited by 11 publications

References 20 publications

Development of Fast Fourier-Compatible Image Reconstruction for 3D Near-Field Bistatic Microwave Imaging With Dynamic Metasurface Antennas

Development of Fast Fourier-Compatible Image Reconstruction for 3D Near-Field Bistatic Microwave Imaging With Dynamic Metasurface Antennas

Towards On-Board SAR Processing with FPGA Accelerators and a PCIe Interface

An integrated FIR adaptive filter design by hybridizing canonical signed digit (CSD) and approximate booth recode (ABR) algorithm in DA architecture for the reduction of noise in the sensor nodes

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