Adaptive Multi-Level Active Gate Drivers for SiC Power Devices

Zhao, Shuang; Dearien, Audrey; Wu, Yuheng; Farnell, Chris; Rashid, Arman Ur; Luo, Fang; Mantooth, H. Alan

doi:10.1109/tpel.2019.2922112

Cited by 102 publications

(41 citation statements)

References 30 publications

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“…Meanwhile, we must notice the load current and bus voltage (output power) will influence the switching performance [25]. In other words, even for the same power device, coupling effects between drain loop and gate driver loop by dv DS /dt could be different under different operation conditions.…”

Section: Experimental Results and Comparisonmentioning

confidence: 99%

“…Reference [24] investigated the influence of parasitic element of a discrete SiC MOSFET device on the switching performance, especially on drain-source voltage (v DS ) characteristics at turn-on transient. Reference [25,26] investigated the effects of increasing load current/output power on Miller plateau voltage and turn-off transient. It is concluded that the output power has great influence on the characteristics of drain current (i DS ), drain-source voltage (v DS ), and gate-source voltage (v gs ) at turn-off transients.…”

Section: Introductionmentioning

confidence: 99%

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Modeling and Analysis of vgs Characteristics for Upper-Side and Lower-Side Switches at Turn-on Transients for a 1200V/200A Full-SiC Power Module

et al. 2019

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In this work, a 1200V/200A full-SiC half-bridge power module was fabricated for high-power high-frequency application, and the characteristics of gate-source voltage ( v g s ) at turn-on transient under different output power was investigated via experiments, modeling, and simulation. Also, the comparison of the v g s characteristics between the upper-side and lower-side was conducted. From experiments, the v g s characteristics show negative spike issue and it becomes severe under higher output power conditions. On the other hand, the upper-side and lower-side show different characteristics, namely, the v g s spike of upper-side is superimposed by a 83.3 MHz high frequency oscillation during the process of v g s being pulled down, while the v g s spike of lower-side contains no oscillation. The mechanisms behind the influence of output power on the v g s spike characteristics and their difference between the upper-side and lower-side were studied via modeling and simulation. Equivalent RLC (resistance-inductance-capacitance) circuit models were proposed and established for the gate driver loops of the upper-side and lower-side based on the internal structure of the power module. With the help of the proposed models, v g s characteristics of the upper-side and lower-side were simulated and compared with the experimental results. The trend of changes in the v g s pulling-down and oscillation amplitude along with the increasing output power from simulation are consistent with that of the experimental results. In addition, different conditions of gate resistance for the SiC power module are compared. Through the comparison between the experiments and simulations, the validity of the proposed equivalent RLC circuit model and the rationality of the analysis about the mechanisms behind the v g s characteristics at turn-on transient for SiC half-bridge power module are confirmed.

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Section: Experimental Results and Comparisonmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Modeling and Analysis of vgs Characteristics for Upper-Side and Lower-Side Switches at Turn-on Transients for a 1200V/200A Full-SiC Power Module

et al. 2019

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“…In addition to the general model categories investigated in Table I, there are many specialized models that have been developed for specific purposes. For example, trajectory based models, which are behavioral descriptions of the capacitance during transient operation, have been presented for development of active-gate drive technology [33], [34]. Such models are suitable since high local accuracy can be achieved with low computational penalty, which makes them ideal for deployed use on microcontrollers.…”

Section: A Capacitance Models 1 Drain To Gate Capacitancementioning

confidence: 99%

Computational Efficiency Analysis of SiC MOSFET Models in SPICE: Dynamic Behavior

Nelson

Lemmon

Jimenez

et al. 2021

IEEE Open J. Power Electron.

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Transient simulation of complex converter topologies is a challenging problem, especially in detailed analysis tools like SPICE. Transistor models presented for SPICE are often evaluated by accuracy, with less consideration for the computational cost of model elements. In order to optimize models for application simulations, this research quantifies the relative simulation performance of modeling approaches and contextualizes the results with regard to accuracy. It is well established that the primary contributor to semiconductor dynamic behavior is the voltage-dependent interelectrode capacitances. Therefore, this study isolates these model components to resolve their influence on model accuracy and runtime. Both the voltage-dependencies modeled, and the mathematic formulation chosen strongly influence the accuracy of interelectrode capacitance models. In addition to these factors, the specific implementation chosen within SPICE also determines simulation performance. Through careful evaluation of these factors, this study offers specific recommendations for optimal implementations of interelectrode capacitances in SPICE.

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“…Other attempts for multilevel gate drivers have been presented in the literature, mainly with discrete solutions [4][5][6][7][8][9][10], while active gate drivers focused on improved switching loss -EMI tradeoff [11,12] or short circuit protection [13]. The core idea here is to cascade 5V CMOS push-pull circuits in series, each being supplied by the energy stored in 5V floating capacitors (Fig reduced to +12V during turn-on, the peak gate current is maintained high to guarantee high switching speeds and low SiC switching losses thanks to a lower gate resistance than the one in classical 2-level operation.…”

Section: Classical Topologymentioning

confidence: 99%

Modular Multilevel SOI-CMOS Active Gate Driver Architecture for SiC MOSFETs

Rouger

Barazi

Cousineau

et al. 2020

2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD)

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High Voltage SiC power MOSFETs have specific driving challenges such as a reduced short circuit capability (compared to Si IGBTs) and a weak field oxide layer, a large gate to source driving voltage (compared to GaN FETs), a high electric field under negative gate bias in off-state and a high switching speed. The negative bias in off-state creates a high stress which reduces the reliability of the SiC MOSFET. The high positive gate bias can generate large drain saturation current in case of short circuit events. We propose a modular multilevel architecture, which takes benefits of SOI isolation and low voltage CMOS transistors to drive SiC MOSFETs and to improve their reliability using an active and dynamic multilevel-selection on the switching sequences and on/off states.

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Adaptive Multi-Level Active Gate Drivers for SiC Power Devices

Cited by 102 publications

References 30 publications

Modeling and Analysis of vgs Characteristics for Upper-Side and Lower-Side Switches at Turn-on Transients for a 1200V/200A Full-SiC Power Module

Modeling and Analysis of vgs Characteristics for Upper-Side and Lower-Side Switches at Turn-on Transients for a 1200V/200A Full-SiC Power Module

Computational Efficiency Analysis of SiC MOSFET Models in SPICE: Dynamic Behavior

Modular Multilevel SOI-CMOS Active Gate Driver Architecture for SiC MOSFETs

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