Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores

Laffely, A.J.; Liang, Jian; Tesseir, R.; Burleson, Wayne

doi:10.1109/icip.2003.1247192

Cited by 11 publications

(7 citation statements)

References 15 publications

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“…aSOC [22], [21] implements the same type of static TDM schedule found in AEthereal, but it does not implement the actual end-to-end connections, leaving this task to the IPs.…”

Section: Related Workmentioning

confidence: 99%

dAElite: A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up

Stefan

Molnos

Goossens

2014

IEEE Trans. Comput.

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Networks-on-Chip are seen as promising interconnect solutions, offering the advantages of scalability and high frequency operation which the traditional bus interconnects lack. Several NoC implementations have been presented in the literature, some of them having mature tool-flows. The main differentiating factor between the various implementations are the services and communication patters they offer to the end-user. In this paper we present dAElite, a TDM Network-on-Chip that offers a unique combinations of features, namely guaranteed bandwidth and latency per connection, built-in support for multicast, and a short connection setup time. While our NoC was designed from the ground up, we leverage on existing tools for network dimensioning, analysis and instantiation. We have implemented and tested our proposal in hardware and we compared it to AEthereal, a state-of-theart NoC with similar features, but no multicast. We find that the connection setup time is reduced by a factor of 10 and the network traversal latency is decreased by 33%. Moreover, considering realistic values of the network parameters dAElite has a lower hardware area when synthesized in 65 nm technology.

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“…aSOC [22], [21] implements the same type of static TDM schedule found in AEthereal, but it does not implement the actual end-to-end connections, leaving this task to the IPs.…”

Section: Related Workmentioning

confidence: 99%

dAElite: A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up

Stefan

Molnos

Goossens

2014

IEEE Trans. Comput.

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“…TDM-based NoC architectures are presented in [5,10,11]. However, only [5] address the resource allocation on such architectures.…”

Section: Related Workmentioning

confidence: 99%

“…We exploit knowledge of the partial path π p traversed so far and determine contention cost for a channel c by how much t(c) reduces the amount of available slots compared to t(π p ) if c is traversed. Discretized available bandwidth is incorporated by taking the maximum of the two as contention measure, according to (11).…”

Section: Choice Of Cost Functionmentioning

confidence: 99%

A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic

2007

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One of the key steps in Network-on-Chip-based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problems first map cores onto a topology and then route communication, using separate and possibly conflicting objective functions. In this paper, we present a unified single-objective algorithm, called Unified MApping, Routing, and Slot allocation (UMARS+). As the main contribution, we show how to couple path selection, mapping of cores, and channel time-slot allocation to minimize the network required to meet the constraints of the application. The time-complexity of UMARS+ is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder System-on-Chip, reducing area by 33%, power dissipation by 35%, and worst-case latency by a factor four over a traditional waterfall approach.

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“…aSOC [19], [18] implements the same type of static TDM schedule found in AEthereal, but it does not implement the actual end-to-end connections, leaving this task to the IPs.…”

Section: Introductionmentioning

confidence: 99%

A TDM NoC supporting QoS, multicast, and fast connection set-up

Stefan

Molnos

Ambrose

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-Networks-on-Chip are seen as promising interconnect solutions, offering the advantages of scalability and high frequency operation which the traditional bus interconnects lack. Several NoC implementations have been presented in the literature, some of them having mature tool-flows and ecosystems. The main differentiating factor between the various implementations are the services and communication patters they offer to the enduser. In this paper we present dAElite, a TDM Network-on-Chip that offers a unique combinations of features, namely guaranteed bandwidth and latency per connection, built-in support for multicast, and a short connection set-up time. While our NoC was designed from the ground up, we leverage on existing tools for network dimensioning, analysis and instantiation. We have implemented and tested our proposal in hardware and we found it to compare favorably to the other NoCs in terms of hardware area. Compared with aelite, which is closest in terms of offered services our network offers connection set-up times faster by a factor of 10 network, traversal latencies decreased by 33%, and improved bandwidth.

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Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores

Abstract: For motion estimation (ME) and discrete cosine transform (DCT)

Cited by 11 publications

References 15 publications

dAElite: A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up

dAElite: A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up

A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic

A TDM NoC supporting QoS, multicast, and fast connection set-up

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