Adaptive Wafer Scale Integration

Abstract

Based on an in-situ electrical alterable nonvolatile semiconductor memory, the MNOS transistor, an adaptive interconnect is developed to implement wafer-scale integration. Experimental validation of the interconnect is reported. The interconnect concept is further extended to the design of semiconductor mass memory and the design of an adaptive voter to implement fault tolerant systems.

Addressable WSI: a non-redundant approach

“…The early efforts with static WSI largely concentrated on logic while recent work has focused on memory modules [5][6][7][8][9][10][11] as well. Several problems are associated with logic WSI -excessive pinouts, high power, low efficiency, and utility.…”

“…To overcome these difficulties other efforts have focused on dynamic configuration [6,7] in which active logic is used to configure circuits on the wafer (nonvolatile configuration [8] could be construed as a variation of dynamic technologies). Of course, with dynamic configuration either the status of the wafer must be stored on permanent media whenever power is removed, or retesting and reconfiguration must occur when repowering the system.…”

Configuration of VLSI Arrays in the Presence of Defects

“…Integrated switches that can be permanently opened or dosed by a laser [17,21,25], and even nonvolatile electrically reprogrammable switches [14,23] have been fabricated. These techniques are being used to develop memory systems that occupy an entire silicon wafer [14] and "restructurable" wafer-scale processor arrays [ 17].…”