Advanced 3D chip stack process for thin dies with fine pitch bumps using pre-applied inter chip fill

Horibe, Akihiro; Yamada, Fumiaki

doi:10.1109/3dic.2009.5306555

Cited by 5 publications

(6 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Characterization of micro-bumps for silicon carrier applications was carried out by Wright et al [52], who concluded that contact resistance was found to be about the same for eutectic SnPb as well as SnCu solder compositions, and at most 2-3 times larger than the standard 100 µm bumps. Further work in this field has been conducted by others [53][54][55]. Thus, although microbumps are not mandated for all 3D die stacking, their importance will increase in proportion to the requirement of having a tightly packed grid of interconnections between opposing die.…”

Section: Micro Bump Technologymentioning

confidence: 95%

3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

View full text Add to dashboard Cite

3-D integration delivers value by increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. Several researchers have studied various aspect of 3Di such as bonding level, through silicon via processes and integration, thermomechanical reliability of the vias, and the impact of the vias on devices. In this paper, we review some of the literature with a view to understanding the key options and challenges in 3Di. We also discuss some important applications of this technology, and the constraints that have to be overcome to make it work.

show abstract

Section: Micro Bump Technologymentioning

confidence: 95%

3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

View full text Add to dashboard Cite

show abstract

“…1). The relationship between refraction coefficients and reflection coefficients can be formulated as (1).…”

Section: System Modelmentioning

confidence: 99%

“…Considering that the complete refraction and reflection process of the path in 3DWiNoC is complex and difficult to completely and clearly described, the modeling can be implemented in the following order (1)(2)(3).…”

Section: System Modelmentioning

confidence: 99%

“…Referring to ( 7) and ( 8), ( 27) can be written as: Referring to (3) and ( 4), (28) can be written as: which can be easily derived by (1).…”

Section: Appendix a Proof Of Computation Complexitymentioning

confidence: 99%

“…In recent years, the number of cores and threads in chips of mobile devices has been increasing to meet the requirement of Internet of Things (IoT). To reduce the area overhead, 3D integration technology are widely used in IoT memory devices [1]. However, the increase of through-silicon-vias (TSV) density in 3D chips leads to higher wiring complexity as well as higher cost of wired communication between cores [2].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

3D Wireless Channel Modeling for Multi-layer Network on Chip

Ren,

Hou,

Pan

2021

Preprint

View full text Add to dashboard Cite

The resource constraints and accuracy requirements for Internet of Things (IoT) memory chips need threedimensional (3D) monolithic integrated circuits, of which the increasing stack layers (currently more than 176) also cause excessive energy consumption and increasing wire length. In this paper, a novel 3D wireless network on chips (3DWiNoCs) model transmitting signal directly to the destination in arbitrary layer is proposed and characterized. However, due to the the reflection and refraction characteristics in each layer, the complex and diverse wireless paths in 3DWiNoC add great difficulty to the channel characterization. To facilitate the modeling in massive layer NoC situation, both boundary-less model boundaryconstrained 3DWiNoC model are proposed, of which the channel gain can be obtained by a computational efficient approximate algorithm. These 3DWiNoC models with approximation algorithm can well characterize the 3DWiNoC channel in aspect of complete reflection and refraction characteristics, and avoid massive wired connections, high power consumption of crosslayer communication and high-complexity of 3DWiNoC channel characterization. Numerical results show that: 1) The difference rate between the two models is lower than 0.001% (signal transmit through 20 layers); 2) the channel gain decreases sharply if refract time increases; and 3) the approximate algorithm can achieve an acceptable accuracy (error rate lower than 0.1%).

show abstract