Advanced Low-Power Digital Circuit Techniques

Elrabaa, Muhammad S.; Abu-Khater, Issam S.; Elmasry, M.I.

doi:10.1007/978-1-4419-8546-0

Cited by 27 publications

(10 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This is because of using two sets of regular CPL adders in regular design (or) one set of regular CPL adder and one set of CPL BEC block in design using BEe. Regular CPL adder proposed [8] takes more number of transistors to design the functionality when compare with the traditional designs. Then this problem leads to designing of an area efficient, fast and low power design by modifying internal structure of 4 bit regular CPL adder to eliminate second block (RCAICPLA/BEC) in carry select adder.…”

Section: [2]mentioning

confidence: 99%

See 1 more Smart Citation

Low-power and high speed CPL-CSA adder

Boppana

Ren

Chen

2014

NAECON 2014 - IEEE National Aerospace and Electronics Conference

View full text Add to dashboard Cite

High speed, low power, area efficient adders continue to play a key role in hardware implementations of digital signal processing applications. Adders based on Complimentary Pass Transistor Logic (CPL) are power and area efficient, but are slower compared to Square Root Carry Select (SQRT-CS) based adders. This paper proposes a unique custom adder design in 2S0-nm CMOS technology, which is based on a combination of CPL and CS logic to obtain a fast and power/area efficient adder design. A 16 bit CPLICS adder is presented which is faster compared to the standard SQRT CS adder while significantly reducing the power and area.

show abstract

Section: [2]mentioning

confidence: 99%

“…It generates sum (SO), carry (CO) and its dual (C1) as well as the complimentary signals (SO', CO', C1 '). P, Q, R, S Sub blocks of Block1 and Blocks 2 enclosed in left side dotted rectangle of 4 bit Regular CPL adder[8] shown inFig. 3 generates S[O], S[l], C[1], C[1]' respectively.…”

mentioning

confidence: 99%

Low-power and high speed CPL-CSA adder

Boppana

Ren

Chen

2014

NAECON 2014 - IEEE National Aerospace and Electronics Conference

View full text Add to dashboard Cite

show abstract

“…It increases time delays as power gated modes have to be safely entered and exited [12]. The possible amount of leakage power saving in such low power mode and the energy dissipation to enter and exit such mode introduces some architectural trade-offs.…”

Section: A Power Gatingmentioning

confidence: 99%

AREA and power optimized multipliers with minimum leakage

Rani¹,

Rao

2011

2011 3rd International Conference on Electronics Computer Technology

View full text Add to dashboard Cite

In this work, we designed a 10 transistor full adder for low power which is used in the implementation of different types of multipliers. All these multipliers are compared for different technologies 90nm, 70nm, 50nm. A power gating technique is used by placing an MTCMOS cell is used at fine grain level so as to minimize the leakage power. Multiplier is an essential arithmetic component for any DSP application, such as filtering and fast Fourier transform (FFT). To achieve high execution speed, parallel array multipliers are widely used. These multipliers tend to consume most of the power in DSP computations, and thus power-efficient multipliers are very important for the design of low-power DSP systems. Two Components contribute to the power dissipation in CMOS circuits. The Static dissipation is due to leakage current, while dynamic power dissipation is due to switching transient current as well as charging and discharging of load capacitances.

show abstract

“…A Wallace tree would lead, in general, to larger power dissipation and area, due to the interconnect wires. Hence, it is not recommended for low power consumption applications [10], [11]. Therefore, we have chosen an array multiplier for 1-D FIR computations due to its popular usage in image processing.…”

Section: B Disadvantages Of a Static Array Multiplier With Highly Comentioning

confidence: 99%

A low-power array multiplier using separated multiplication technique

Han

Park

Kim

2001

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

This brief proposes a separated multiplication technique that can be used in digital image signal processing such as finite impulse response (FIR) filters to reduce the power dissipation. Since the 2-D image data have high spatial redundancy, such that the higher bits of input pixels are hardly changed, the redundant multiplication of higher bits is avoided by separating multiplication into higher and lower parts. The calculated values of the higher bits are stored in memory cells, caches, such that they can be reused when a cache hit occurs. Therefore, the dynamic power is reduced by about 14% in multipliers by using the proposed separated multiplication technique (SMT) and in a 1-D 4-tap FIR filter by about 10%.Index Terms-FIR filter, low power, LRU, multiplier.

show abstract

Advanced Low-Power Digital Circuit Techniques

Cited by 27 publications

References 0 publications

Low-power and high speed CPL-CSA adder

Low-power and high speed CPL-CSA adder

AREA and power optimized multipliers with minimum leakage

A low-power array multiplier using separated multiplication technique

Contact Info

Product

Resources

About