Advanced scalable ultralow-k/cu interconnect technology for 32 nm CMOS ULSI using self-assembled porous silica and self-aligned CoWP barrier

Abstract

An advanced scalable Cu damascene process was developed using self-assembled porous silica with tetramethylcyclotetrasiloxane (TMCTS) treatment and selective electroless plating of Cu barrier. It is found that the TMCTS vapor treatment could recover process-induced damages after plasma ashing and chemical mechanical polishing, resulting in no line-width dependence of the effective dielectric constant of the porous silica films. Furthermore, the selective electroplating of CoWP on Cu interconnects could suppress Cu drift and improve time-dependent dielectric breakdown of the porous silica film. IntroductionThe performance of MOS transistors has been improved by introducing the scaling rule to the device dimension [1]. On the contrary, the performance of the interconnects in signal delay has been degraded by scaling multilevel interconnect dimensions due to the parasitic capacitances and resistances [2]. Therefore, the interlayer dielectric films with ultralow dielectric constants (k) are needed for ultrahigh-speed digital integrated circuits and radio-frequency mixed-signal circuits to reduce parasitic capacitances of metal interconnects. However, further reduction in k values requires more porosity in the low-k film, resulting in elastic modulus reduction. To solve the reduction of mechanical strength, we have developed scalable self-assembled porous silica films and tetramethylcyclotetrasiloxane (TMCTS) vapor treatment that could improve the elastic modulus of the porous silica film [3][4][5]. Ultralow-k porous silica film is also sensitive to process-induced damages caused by plasma ashing and wet chemical processes. It is necessary to develop damage-less processes or recover the process-induced damages in porous silica films [6]. The purpose of this work is to develop an advanced ultralow-k porous-silica/Cu damascene process that can achieve damage-free and scalable low-k properties with self-aligned Cu barrier metal for 32 nm CMOS ULSI.

Pure Silica Zeolite Films Prepared by a Vapor Phase Transport Method

“…Preparation of pure silica zeolite films consisted of a solgel technique based on the self-assembling of surfactant templates, 1,2) and the VPT method. 5) A precursor solution was prepared using silica precursor tetraethoxysilane (TEOS), catalyst nitric acid, water, and solvent ethanol.…”

“…Mesoporous silica films have been proposed as promising candidates for ultra low-k dielectrics with dielectric constants of less than 2.1. 1,2) However, they have lower mechanical strength as porosity increases because their skeletal structure, which is composed of amorphous silica, becomes thinner. Recently, much attention has been paid to mesoporous silica films with zeolite components.…”

Wireless Interchip Interconnects

“…A system on a chip (SOC) has been developed because it enables the highest packing density of scaled transistors for building an ultra-large-scale integrated circuit system (ULSI). To solve the RC signal delay problems for advanced CMOS technology, new materials such as copper (Cu) and low dielectric constant (low-k) interlayer dielectric films have been introduced [4,5], as shown in Figure 15.1 (a). To solve the RC signal delay problems for advanced CMOS technology, new materials such as copper (Cu) and low dielectric constant (low-k) interlayer dielectric films have been introduced [4,5], as shown in Figure 15.1 (a).…”

Theoretical Investigation of Maximum Field Strength in Porous Silica Dielectric

“…A porous silica dielectric is a composite dielectric constructed from a silica skeleton and cylindrical air pores with 2 -5 nm in diameter. 1) The field distribution fluctuates in the composite under applied constant electric field. It is known that in these composite dielectrics the dielectric breakdown is initiated at the local spot where the maximum field strength appears.…”