AES-128 Cipher. High Speed, Low Cost FPGA Implementation

Liberatori, M. C.; Otero, Fernando; Bonadero, Juan Carlos; Castiñeira, J.

doi:10.1109/spl.2007.371748

Cited by 29 publications

(7 citation statements)

References 2 publications

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“…AES algorithm throughput can be increased by using folded parallel architecture [13].Through put can be further increased by introducing 2-slow retiming technique [14].A light weight Mix Column structure can be designed using [16]. By using X time based MixColumn transformation the speed circuit can be increased along the reduced area [17][18][19][20][21][22][23][24][25].…”

Section: 1 Related Workmentioning

confidence: 99%

FPGA implementation of AES algorithm for high speed applications

Priya

Karthigaikumar

Teja

2021

Analog Integr Circ Sig Process

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The main objective of this paper is to design and implement High throughput, area efficient AES encryption algorithm on FPGA for security purposes. The high speed and area efficiency is achieved by designing an area efficient and high throughput structural S-Box architecture for AES encryption process. A combinational logic circuit based Rijndael Low area high speed S-Box is designed. The results compared with conventional S-Box. The speed and propagation delay of the S-Box are calculated for the designed S-Box. The proposed S-Box is used in AES encryption process. To further increase the speed of the encryption process efficient structure of Mix column is also proposed. This Mix column structure is used to achieve high throughput. The proposed S-Box and Mix Column are used in AES encryption. This proposed AES structure is implemented in FPGA Virtex 5.The results are compared with the conventional implementation.

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Section: 1 Related Workmentioning

confidence: 99%

FPGA implementation of AES algorithm for high speed applications

Priya

Karthigaikumar

Teja

2021

Analog Integr Circ Sig Process

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“…Liberatori et al . introduced in an architecture for low area 128‐bit AES cipher. This paper presents an 8‐bit FPGA implementation of the 128‐bit block and 128‐bit key AES cipher.…”

Section: Related Workmentioning

confidence: 99%

FPGA implementation of AES algorithm for high throughput using folded parallel architecture

Rahimunnisa

Karthigaikumar

Rasheed

et al. 2012

Security Comm Networks

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This paper presents high throughput architecture for the hardware implementation of Advanced Encryption Standard algorithm. Advanced Encryption Standard is the industry standard crypto algorithm for encryption and is used for protecting secret information. This work is mainly targeted for low‐cost embedded applications. This paper introduces parallel operation in the folded architecture to obtain better throughput. The design is coded in Very High‐speed Integrated Circuit Hardware Description Language. Timing simulation is performed to verify the functionality of the designed circuit. The proposed structure is implemented in Virtex‐6 XC6VLX75T FPGA device. This work gives a high throughput of 37.1 Gb/s with a maximum frequency of 505.5 MHz, which is 20% higher than the maximum throughput reported in the literature. Copyright © 2012 John Wiley & Sons, Ltd.

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“…If high data throughput is required their implementation in hardware, often in configurable devices, is of fundamental importance. Numerous positions in the literature propose particularly efficient hardware implementations of the ciphers ( [3][4][5][6], [8][9][10], [13]) but the aim of this work is different: by providing consistent test methodology we want to compare implementation efficiency of selected three cryptographic algorithms (AES, Salsa20 and Keccak-f[400]) in five hardware organizations (iterative, with loop unrolled and pipelined) and in two different FPGA devices (Spartan-3 and Spartan-6 from Xilinx) -in a total of 30 designs. The text is presented in just two essential parts: the second chapter introduces the selected five hardware organizations viable for round-based ciphers and discusses their particular realizations for the three algorithms, and the third chapter includes the results of implementation and presents their evaluation with regard to efficiency offered by the two platforms, scalability of the ciphers with the loop unrolling factor and specific routing problems of some configurations.…”

Section: Introductionmentioning

confidence: 99%

Popular FPGA Device Families in Implementation of Cryptographic Algorithms

Sugier

2015

Advances in Intelligent Systems and Computing

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Abstract. This work evaluates implementation efficiency of different cryptographic algorithms in selected hardware organizations and in different FPGA devices. The tests included AES symmetric cipher and two more contemporary hash algorithms: Salsa20 and Keccak-f[400] permutation function. Each algorithm was realized in hardware in five organizations: the basic iterative one, two with the loop unrolled and two with the loop unrolled and pipelined, then automatically implemented in two popular-grade FPGA devices from Xilinx: Spartan-3 and Spartan-6. Results of 30 test cases allowed for evaluation of particular strengths and weaknesses of the ciphers, the organizations and the FPGA architectures. In particular, the evaluation took into account implementation efficiency offered by the two device families, scalability of the ciphers with the loop unrolling factor and specific routing problems which came out in some configurations.

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AES-128 Cipher. High Speed, Low Cost FPGA Implementation

Cited by 29 publications

References 2 publications

FPGA implementation of AES algorithm for high speed applications

FPGA implementation of AES algorithm for high speed applications

FPGA implementation of AES algorithm for high throughput using folded parallel architecture

Popular FPGA Device Families in Implementation of Cryptographic Algorithms

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