The realization of Ge gate stacks with thin equivalent oxide thickness (EOT), low interface state density (D it) and small hysteresis is a crucial issue for Ge CMOS. In this study, we propose a new AlYO 3 /GeO x /Ge MOS interface, formed by atomic layer deposition (ALD) AlYO 3 /Ge MOS structures with plasma post oxidation (PPO). Reduction in D it by PPO is found for AlYO 3 /Ge system. A 1.5-nm-thick AlYO 3 /GeO x /Ge interface with 1.25-nm EOT can provide a lower amount of the slow trap density, particularly in the valence band side of Ge, than the control Al 2 O 3 /GeO x /Ge interface and the Y 2 O 3 /GeO x /Ge interface. Deposition of any high-k films on the AlYO 3 /GeO x /Ge structure leads to the increase in the slow trap density to the same level, suggesting the influence of any traps at the interface between the high-k films and AlYO 3 .