Ammonium Hydroxide Effect on Low-Temperature Wafer Bonding Energy Enhancement

Abstract

A wafer prebonding treatment by ammonium hydroxide (NH 4 OH) leading to a high bonding strength at low temperatures is presented in three material systems. After 200°C annealing, a surface energy of about 700 mJ/m 2 for thermal silicon-oxide bonding and of 1300 mJ/m 2 for plasma-enhanced chemical vapor deposition oxide bonding is realized. It is suggested that the lower ability of ammonia, the by-product of a polymerization reaction, to break the siloxane (Si-O-Si) bridging bonds appears to be responsible for the increase in surface energy in both silicon oxide bonding cases. NH 4 OH treatment is also effective on bare germanium/ silicon-oxide bonding with a surface energy of 800 mJ/m 2 . A highly hydrophilic germanium surface obtained by this treatment accounts for the high bonding energy.As transistors are continuously scaled down, new materials and novel device/circuit structures have been suggested for further improvement of their electronic performance. Germanium on insulator ͑GeOI͒ 1-4 and three-dimensional integrated circuits 5,6 are among the most frequently discussed ones. GeOI has drawn much attention for its enhanced low field electron and hole mobility and minimization of parasitic capacitance compared to its conventional bulk silicon counterpart. However, the poor properties of germanium oxide make it unsuitable as buried insulator compared to silicon oxide. The cost of germanium and its brittleness also suggests silicon as the ideal substrate for GeOI wafers. Wafer bonding is one of the promising technologies for achieving this Ge/SiO 2 /Si structure because of its flexibility in combining dissimilar materials. To avoid de-bonding in later processes such as Smart-Cut or chemical mechanical planarization ͑CMP͒, proper cleaning to obtain hydrophilic surfaces and hightemperature annealing are essential to achieve a high bonding energy. Germanium is known for its sensitivity to chemical solutions. The mismatch of thermal expansion coefficients between Si and Ge also complicates any subsequent thermal annealing processes. All these limitations make new approaches to the bonding of bare Ge/ thermally oxidized Si highly desirable.Chemical vapor deposited ͑CVD͒ oxides offer an alternative route to the fabrication of GeOI. With CVD oxide deposition on Ge, the bonding interface would be SiO 2 /SiO 2 for which reliable cleaning processes are available. SiO 2 /SiO 2 bonding is also of technological importance because silicon oxide is widely used for planarization in integrated circuits or as a masking material in the lithography process. Bonding of fully processed wafers is becoming a field of interest especially in the area of system-on-a-chip ͑SOC͒. 7 It is well known that SiO 2 /SiO 2 bonding yields a substantially lower bonding energy than bare silicon bonding because of the difficulty of removing water existing at the bonding interface. The existing water molecules attack newly formed siloxane bonds and decrease the bonding energy. 8 Though higher temperature annealing achieves a high bonding energy, low-t...

III‐V/silicon photonics for on‐chip and intra‐chip optical interconnects

“…After mating the two substrates at room temperature via relatively poor Van der Waals forces or hydrogen bonds, the well-known chemical reactions in Si-based hydrophilic bonding given in Eqs. (1) and (2) start forming strong covalent bonds [19], Figure 1 (online color at: www.lpr-journal.org) Schematic of the O2 plasma-assisted low-temperature III-V-to-Si bonding process flow. a process accelerated by further annealing at elevated temperature (300°C in this work).…”

“…Immediately after the O 2 plasma surface treatment, the second surface activation step is to dip the SOI and III-V samples in a very dilute HF solution (0.025 percent) for 1 min to form a more porous fluorinated oxide network [23]. The last activation step involves further converting Si-OH to Si-NH 2 bonds in NH 4 OH [19,24].…”

Low-Temperature, Strong SiO2-SiO2 Covalent Wafer Bonding for III–V Compound Semiconductors-to-Silicon Photonic Integrated Circuits

“…28 The last activation step involved further conversion of Si-OH to Si-NH 2 bonds in NH 4 OH. 28,29 Instead of dipping the samples in NH 4 OH solution directly, 29 an NH 4 OH vaporization process was found to result in a more uniform and cleaner surface activation. The SOI and III-V samples were placed on a 125°C hotplate with a glass cover for 5 min to reduce the H 2 O monolayers on the sample surface while NH 4 OH vapor was introduced simultaneously.…”

(Invited) GOI Substrates: Fabrication and Characterization

“…The presence of insulators improves the performance of MOSFETs due to the reduction of parasitic capacitance and enables an electrostatic control which is indispensable when downscaling the MOSFET dimensions. There are several methods for fabricating GOI substrates, such as wafer bonding (1)(2)(3)(4)(5)(6)(7)(8), Ge condensation (9)(10)(11), liquid-phase epitaxy (12,13), and separation by implanting oxygen (14,15). Among these methods, a wafer bonding technique using both Si wafers covered with SiO 2 layers and Ge wafers has an advantage that high crystalline quality of Ge layer is potentially accomplished, comparable to that of bulk Ge crystal.…”