Amplifier-Free Bias-Free Receiver Based on Low-Capacitance Nanophotodetector

Nozaki, Kengo; Matsuo, Shinji; Shinya, Akihiko; Notomi, Masaya

doi:10.1109/jstqe.2017.2777105

Cited by 17 publications

(9 citation statements)

References 45 publications

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“…We note that the gain range considered in Fig. 4(a) is well within the regime of what has been demonstrated in integrated transimpedance amplifiers for optical receivers [24][25][26]. In fact, many of these systems have demonstrated much higher gain.…”

Section: γ Lsupporting

confidence: 72%

“…3, the optical source to the ONN would then need to supply N · 0.1 mW of optical power. The power consumption of integrated optical receiver amplifiers varies considerably, ranging from as low as 10 mW to as high as 150 mW [24][25][26], depending on a variety of factors which are beyond the scope of this article. Therefore, a conservative estimate of the power consumption from the optical-to-electrical conversion circuits in all activations is L · N · 100 mW.…”

Section: A Power Consumptionmentioning

confidence: 99%

“…However, the components of the transimpedance amplifier may be challenging to integrate in the area available between neighboring output waveguides of the interferometer mesh. One possibility towards achieving a fully integrated optoelectronic ONN would be to use so-called amplifier-free optical receivers [26], where ultra-low capacitance detectors provide high-speed opto-electronic conversion. Similarly to the experimental demonstration in Ref.…”

Section: Physical Footprintmentioning

confidence: 99%

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Reprogrammable Electro-Optic Nonlinear Activation Functions for Optical Neural Networks

Williamson

Hughes

Minkov

et al. 2020

IEEE J. Select. Topics Quantum Electron.

250

140

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We introduce an electro-optic hardware platform for nonlinear activation functions in optical neural networks. The optical-to-optical nonlinearity operates by converting a small portion of the input optical signal into an analog electric signal, which is used to intensity-modulate the original optical signal with no reduction in processing speed. Our scheme allows for complete nonlinear on-off contrast in transmission at relatively low optical power thresholds and eliminates the requirement of having additional optical sources between each layer of the network. Moreover, the activation function is reconfigurable via electrical bias, allowing it to be programmed or trained to synthesize a variety of nonlinear responses. Using numerical simulations, we demonstrate that this activation function significantly improves the expressiveness of optical neural networks, allowing them to perform well on two benchmark machine learning tasks: learning a multi-input exclusive-OR (XOR) logic function and classification of images of handwritten numbers from the MNIST dataset. The addition of the nonlinear activation function improves test accuracy on the MNIST task from 85% to 94%.

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Section: γ Lsupporting

confidence: 72%

Section: A Power Consumptionmentioning

confidence: 99%

Section: Physical Footprintmentioning

confidence: 99%

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Reprogrammable Electro-Optic Nonlinear Activation Functions for Optical Neural Networks

Williamson

Hughes

Minkov

et al. 2020

IEEE J. Select. Topics Quantum Electron.

250

140

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show abstract

“…7 and Supplementary Note 4), and we found that the operation bit rate is basically limited by the rise and fall time of the optical input signals. The power consumption can be reduced down to sub fJ/ bit order by integrating nanophotodetectors with much smaller capacitance 27 or by employing much higher bit rate >100 Gbps.…”

Section: Discussionmentioning

confidence: 99%

Ultrashort low-loss Ψ gates for linear optical logic on Si photonics platform

et al. 2020

Self Cite

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Nonlinear optical gates are usually considered as fundamental building blocks for universal optical computation. However, the performance is severely limited by small optical nonlinearity, thereby bounding their operation speed, consumption energy, and device size. In this paper, we propose and experimentally demonstrate linear optical logic operations with 3 μm-long Si wire "Ψ" gates consist of 3 × 1 optical combiners including auxiliary bias port, which maximizes the binary contrast of the output in telecom wavelength. We have demonstrated 20 Gbps Boolean "AND" operation with experimentally measured small signal loss (1.6 dB experimentally). A single Ψ gate can perform representative Boolean operations by changing the bias power and relative phases. We have also demonstrated wavelengthindependent operation by seven wavelengths, which leads to wavelength-division multiplexed parallel computation. This ultrashort, highly-integrable, low-loss, and energy-efficient optical logic gates pave the way for ultralow latency optical pattern matching, recognition, and conversion.

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“…Alignment for the multilayer exposure is a standard procedure in the semiconductor device fabrication process, and the level of alignment accuracy needed for the advanced photonic integrated devices is very high. This may be for embedding gain material into the photonic crystal cavities and waveguides for lasers [11], modulators [12] and photodetectors [13], contacts for electrical operation of such devices [14], light coupling to/from active III-V layer into passive Si circuitry [15], or even combinations of these. Many factors can, through the complex wafer geometry changes (arising from deposition of films with nonuniform residual stress or bonding [16], in-plane stretching deformations induced by wafer chucking during lithography [17]), alter initially defined device patterns and their relative positions to alignment marks during wafer processing in-between exposure steps.…”

Section: Introductionmentioning

confidence: 99%

Comparison of processing-induced deformations of InP bonded to Si determined by e-beam metrology: Direct vs. adhesive bonding

Sakanas

Semenova

Ottaviano

et al. 2019

Microelectronic Engineering

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In this paper, we employ an electron beam writer as metrology tool to investigate distortion of an exposed pattern of alignment marks in heterogeneously bonded InP on silicon. After experimental study of three different bonding and processing configurations which represent typical on-chip photonic device fabrication conditions, the smallest degree of linearly-corrected distortion errors is obtained for the directly bonded wafer, with the alignment marks both formed and measured on the same InP layer side after bonding (equivalent to single-sided processing of the bonded layer). Under these conditions, multilayer exposure alignment accuracy is limited by the InP layer deformation after the initial pattern exposure mainly due to the mechanical wafer clamping in the e-beam cassette. Bonding-induced InP layer deformations dominate in cases of direct and BCB bonding when the alignment marks are formed on one InP wafer side, and measured after bonding and substrate removal from another (equivalent to double-sided processing of the bonded layer). The findings of this paper provide valuable insight into the origin of the multilayer exposure misalignment errors for the bonded III-V on Si wafers, and identify important measures that need to be taken to optimize the fabrication procedures for demonstration of efficient and high-performance on-chip photonic integrated devices.

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Amplifier-Free Bias-Free Receiver Based on Low-Capacitance Nanophotodetector

Cited by 17 publications

References 45 publications

Reprogrammable Electro-Optic Nonlinear Activation Functions for Optical Neural Networks

Reprogrammable Electro-Optic Nonlinear Activation Functions for Optical Neural Networks

Ultrashort low-loss Ψ gates for linear optical logic on Si photonics platform

Comparison of processing-induced deformations of InP bonded to Si determined by e-beam metrology: Direct vs. adhesive bonding

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