An 0.8 µm 256K BiCMOS SRAM technology

Abstract

Semiconductor Process and Design CenterTexas Instruments, Incorporated Dallas, TexasThis paper describes an 0.8 um,BiCMOS process technology for the next generation of very high performance, low power logic and memory roducts.As an example, this technology is

Circuit techniques for large CSEA SRAMs

“…These techniques are utilized to enhance the performance of a hypothetical 64K x 4 CSEA SRAM which could be integrated in a O.S-pm (7-GHz~~) BiCMOS technology [9]. Six-bit (1-of-64) diode decoders are chosen for both rows and columns because the resulting 4K X 4 banks provide a good trade-off between individual decoder power and bank selection overhead.…”

“…Because the cell is tolerant of large internal collector resistance (the base of Q1 is never less than 2~~~down from~cc, so the voltage drop across its collector resistor may be this much without saturating Q 1) the~cc wire may be routed on the buried layer of the well/collector and strapped by metal every eight cells or so. For purposes of comparison, a CSEA cell occupying 125 pm2 supplies twice the read current of a 117-pm2 six-transistor (6T) CMOS cell [3] implemented in the same technology [9] . While the access time and density of the CSEA memory make it an attractive candidate for large, fast, on-chip caches, this memory organization is not without its limitations.…”

An overview of BiCMOS technology and applications

“…As a result of this evolution BiCMOS processes wcre based either on CMOS [1][2] or Bipolar 131 process Ilows, resulting in sub-optimal performance for either the bipolar or MOSFET components. In third generation 0 .…”

“…Analog requirements differ in that design rules do not have to be scaled as aggressively; 1.5 -2 p rules suffice for most applications. The challenge of analog is in achieving the proper balance between digital and analog requirements.Numerous approaches to implementing a BiCMOS process have been presented[1][2][3][4][5][6][7][8][9][10][11][12][13][14][15]. A simplified process step sequence comparing BiCMOS to CMOS and Bipolar process flows is shown inTable 111.…”